18376053. LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS (Applied Materials, Inc.)
LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS
Organization Name
Inventor(s)
Sonam Dorje Sherpa of San Ramon CA US
Alok Ranjan of San Ramon CA US
LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS
This abstract first appeared for US patent application 18376053 titled 'LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS
Original Abstract Submitted
Exemplary semiconductor processing methods may include a substrate housed in the processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The methods may include providing a hydrogen-containing precursor, a nitrogen-containing precursor, or both to a processing region of a semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, and contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor. The contacting may remove a portion of the layer of carbon-containing material. The methods may include providing a fluorine-containing precursor to the processing region, forming plasma effluents of the fluorine-containing precursor, and contacting the substrate with the plasma effluents of the fluorine-containing precursor.