18369757. SEMICONDUCTOR WAFER FABRICATION WITH EXPOSURE DEFINED GRAPHENE FEATURES (NXP USA, Inc.)
SEMICONDUCTOR WAFER FABRICATION WITH EXPOSURE DEFINED GRAPHENE FEATURES
Organization Name
Inventor(s)
Douglas Michael Reber of Austin TX US
SEMICONDUCTOR WAFER FABRICATION WITH EXPOSURE DEFINED GRAPHENE FEATURES
This abstract first appeared for US patent application 18369757 titled 'SEMICONDUCTOR WAFER FABRICATION WITH EXPOSURE DEFINED GRAPHENE FEATURES
Original Abstract Submitted
A back-end-of-line integrated circuit is formed on an integrated circuit structure having one or more polymer interlayer dielectric (ILD) layers formed over a first conductive wiring line layer by selectively processing an exposed portion of the one or more polymer ILD layers with application irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer.