CHIPLET INTERCONNECT POWER STATE MANAGEMENT

Organization Name

Advanced Micro Devices, Inc.

Inventor(s)

Nicholas Carmine Defiore of Austin TX (US)

Sridhar Varadharajulu Gada of Austin TX (US)

Benjamin Tsien of Santa Clara CA (US)

YanFeng Wang of Markham (CA)

Steven Zhou of Markham (CA)

Duanduan Chen of Markham (CA)

Malcolm Earl Stevens of Santa Clara CA (US)

CHIPLET INTERCONNECT POWER STATE MANAGEMENT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18336541 titled 'CHIPLET INTERCONNECT POWER STATE MANAGEMENT

The disclosed device for power management of chiplet interconnects involves multiple chiplets connected via multiple interconnects. A control circuit is included to detect the activity states of the chiplets and manage the power states of the interconnects based on the detected activity states.

Multiple chiplets connected via multiple interconnects
Control circuit to detect activity states of chiplets
Power management of interconnects based on activity states
Methods, systems, and computer-readable media disclosed
Efficient power utilization in chiplet interconnects

Potential Applications: - Data centers - High-performance computing - Internet of Things (IoT) devices

Problems Solved: - Power inefficiency in chiplet interconnects - Overheating issues in interconnected chiplets

Benefits: - Improved power efficiency - Enhanced performance of interconnected chiplets - Reduced overheating risks

Commercial Applications: Title: "Efficient Power Management Device for Chiplet Interconnects" This technology can be utilized in data centers, high-performance computing systems, and IoT devices to optimize power usage and enhance overall performance.

Questions about Efficient Power Management Device for Chiplet Interconnects: 1. How does the control circuit detect the activity states of chiplets? 2. What are the potential long-term benefits of implementing this power management device in data centers?

Original Abstract Submitted

The disclosed device for power management of chiplet interconnects includes multiple chiplets connected via multiple interconnects. The device also includes a control circuit that detects activity states of the chiplets and manages power states of the interconnects based on the detected activity states. Various other methods, systems, and computer-readable media are also disclosed.