18334858. ZERO-DETECTION FOR LOGIC CIRCUIT MULTIPLICATION (Microsoft Technology Licensing, LLC)
ZERO-DETECTION FOR LOGIC CIRCUIT MULTIPLICATION
Organization Name
Microsoft Technology Licensing, LLC
Inventor(s)
Evgeny Royzen of Kiryat Ono (IL)
Yaron Baruch Shapiro of Petach Tikva (IL)
ZERO-DETECTION FOR LOGIC CIRCUIT MULTIPLICATION
This abstract first appeared for US patent application 18334858 titled 'ZERO-DETECTION FOR LOGIC CIRCUIT MULTIPLICATION
Original Abstract Submitted
A logic circuit includes an input data line, and a zero-detection element configured to output a latch control signal with a first state based at least in part on detecting that a current input value on the input data line is equal to zero. A latch is configured to receive the current input value and output a latch output value, wherein the latch output value is a prior input value based at least in part on the latch control signal having the first state, and wherein the latch output value is the current input value based at least in part on the latch control signal having a second state. A multiplier performs a multiplication operation based at least in part on the latch output value.