18242232. MEMORY DEVICE AND OPERATING METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
MEMORY DEVICE AND OPERATING METHOD THEREOF
Organization Name
Inventor(s)
Yonghyuk Choi of Suwon-si (KR)
Seungyong Choi of Suwon-si (KR)
MEMORY DEVICE AND OPERATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18242232 titled 'MEMORY DEVICE AND OPERATING METHOD THEREOF
The memory device described in the patent application consists of a memory cell array with multiple cell blocks, including one for storing user data and another for storing information other than user data. Each cell block contains several cell strings and control circuitry to manage write and read operations.
- The first cell block includes a first ground select line (GSL) region with stacked GSLs in a vertical direction, with ground select transistors programmed to different threshold voltages.
- A first line in the first GSL region is positioned at the same height as a word line connected to memory cells storing user data in the second cell block.
- Key Features and Innovation:**
- Memory device with separate cell blocks for user data and other information.
- Ground select transistors with different threshold voltages in the GSL region.
- Strategic positioning of GSL region and word line for efficient memory operations.
- Potential Applications:**
- Data storage devices
- Embedded systems
- Consumer electronics
- Problems Solved:**
- Efficient organization of memory cells
- Enhanced control over memory operations
- Improved data storage capabilities
- Benefits:**
- Optimal data management
- Increased memory efficiency
- Enhanced performance in memory operations
- Commercial Applications:**
- Data storage solutions for various industries
- Memory components for electronic devices
- Potential impact on semiconductor market
- Questions about Memory Device:**
1. How does the programming of ground select transistors affect memory operations? 2. What advantages does the separate cell block design offer in terms of data storage efficiency?
- Frequently Updated Research:**
Ongoing studies on memory cell array optimization and performance enhancements in semiconductor technology.
Original Abstract Submitted
A memory device comprises: a memory cell array including a plurality of cell blocks including a first cell block storing information other than user data and a second cell block storing the user data, wherein each of the plurality of cell blocks includes a plurality of cell strings and control circuitry configured to control a write operation and a read operation of the memory cell array. A first ground select line (GSL) region included in the first cell block includes a plurality of GSLs stacked in a vertical direction. One or more ground select transistors of a plurality of ground select transistors connected to each of the GSLs are programmed to a first threshold voltage and the other ground select transistors of the plurality of ground select transistors not connected to the GSLs are programmed to a second threshold voltage that is higher than the first threshold voltage. A first line included in the first GSL region in the first cell block is arranged at a same height as a word line connected to memory cells storing the user data in the second cell block.