18231284. VERTICAL MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
VERTICAL MEMORY DEVICE
Organization Name
Inventor(s)
Seungyoon Kim of Suwon-si (KR)
VERTICAL MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18231284 titled 'VERTICAL MEMORY DEVICE
Simplified Explanation
The abstract describes a vertical memory device with a unique structure involving a cell stack, through cell contact, and insulation patterns.
- Lower pad pattern on substrate
- Cell stack structure with stepped shape, including insulation layers and gate patterns
- Through cell contact with protrusion contacting uppermost gate pattern
- First insulation pattern surrounding sidewall of through portion
- Protrusion greater in vertical thickness than uppermost gate pattern
Potential Applications
- Data storage devices
- Memory modules
- Solid-state drives
Problems Solved
- Increased memory density
- Enhanced data storage capabilities
- Improved vertical memory device performance
Benefits
- Higher storage capacity
- Faster data access speeds
- More efficient memory utilization
Original Abstract Submitted
A vertical memory device includes: a lower pad pattern disposed on a substrate; a cell stack structure disposed on the lower pad pattern and including first insulation layers and gate patterns, wherein the cell stack structure has a stepped shape; a through cell contact including a first through portion and a first protrusion, wherein the first through portion passes through a portion of the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts an uppermost gate pattern of the gate patterns; and a first insulation pattern at least partially surrounding a sidewall, of the first through portion, that is below the first protrusion, wherein the first insulation pattern is longer than the first protrusion in a horizontal direction from the first through portion, and wherein a vertical thickness of the first protrusion is greater than a vertical thickness of the uppermost gate pattern.