HYBRID METALLIZATION SURFACES FOR INTEGRATED CIRCUIT PACKAGES

Organization Name

Intel Corporation

Inventor(s)

Suddhasattwa Nad of Chandler AZ (US)

Kristof Darmawikarta of Chandler AZ (US)

Jason Steill of Phoenix AZ (US)

Srinivas Pietambaram of Chandler AZ (US)

Marcel Wall of Phoenix AZ (US)

HYBRID METALLIZATION SURFACES FOR INTEGRATED CIRCUIT PACKAGES

This abstract first appeared for US patent application 18216521 titled 'HYBRID METALLIZATION SURFACES FOR INTEGRATED CIRCUIT PACKAGES

Original Abstract Submitted

IC die package with hybrid metallization surfaces. Routing metallization features have lower surface roughness for reduced high-frequency signal transmission losses while IC die attach metallization features have higher surface roughness for greater adhesion. Routing and die attach features may be formed within a same package metallization level, for example with a plating process. An insulator material may be formed over the surface of the metallization features, for example with a dry film lamination process. Optionally, an interface material may be deposited upon at least the routing features to enhance adhesion of the insulator material to metallization surfaces of low roughness. An opening in the insulator material may be formed to expose a surface of a die attach feature. The exposed surface may be selectively roughened, and an IC die attached to the roughened surface.