18216424. LEAKAGE COMPENSATED DYNAMIC LATCH (Intel Corporation)
LEAKAGE COMPENSATED DYNAMIC LATCH
Organization Name
Inventor(s)
Ganesan Iyer of Phoenix AZ (US)
Anupama A. Thaploo of Folsom CA (US)
Ananthakrishnan Ponnileth Rajendran of Rancho Cordova CA (US)
LEAKAGE COMPENSATED DYNAMIC LATCH
This abstract first appeared for US patent application 18216424 titled 'LEAKAGE COMPENSATED DYNAMIC LATCH
Original Abstract Submitted
Some embodiments include input stage of a latch to receive input data information and clock information; a memory node coupled to the input stage to store information based on the input data information; an output stage of the latch coupled to the memory node and including an output node to provide output data information based on the information stored at the memory node; a first circuit to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit to provide a second circuit path between the memory node and a second node in the input stage.