STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Saurabh Shankar Zond of Bengaluru (IN)

Debojyoti Banerjee of Bengaluru (IN)

Abhishek Ghosh of Bengaluru (IN)

Raghavendra Shirodkar of Bengaluru (IN)

Rakesh Dimri of Bengaluru (IN)

Yashaswini H G of Bengaluru (IN)

STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18194894 titled 'STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS

The apparatus described in the patent application includes an integrated circuit with a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit consists of a sum generation circuit for generating a sum output and a carry output generation circuit for generating a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate, while the carry output generation circuit includes a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate.

The FA circuit is designed with a sum generation circuit and a carry output generation circuit.
The sum generation circuit includes two exclusive-NOR gates.
The carry output generation circuit consists of two OAI gates and a NAND gate.
The first OAI gate generates an exclusive-NOR or NOR output of the operands.
The second OAI gate produces the carry output based on the inputs received.

Potential Applications: - This technology can be applied in digital signal processing systems. - It can be used in arithmetic logic units (ALUs) in microprocessors. - The innovation can find applications in computer arithmetic operations.

Problems Solved: - Efficient generation of sum and carry outputs in a full adder circuit. - Improved performance and reliability in digital circuits. - Enhanced functionality in arithmetic operations.

Benefits: - Faster computation speeds in digital systems. - Reduced power consumption in integrated circuits. - Higher accuracy in arithmetic calculations.

Commercial Applications: Title: Integrated Circuit with Static CMOS Based Full Adder Circuit This technology has potential commercial uses in the semiconductor industry for developing advanced digital circuits. It can be utilized in microprocessors, calculators, and other electronic devices requiring fast and reliable arithmetic operations.

Prior Art: Readers can explore prior research on static CMOS based full adder circuits and integrated circuits in digital design textbooks and academic journals.

Frequently Updated Research: Researchers are constantly exploring new techniques to enhance the performance of integrated circuits and digital systems. Stay updated on the latest advancements in CMOS technology and digital circuit design for potential improvements in full adder circuits.

Questions about Integrated Circuit with Static CMOS Based Full Adder Circuit: 1. How does the FA circuit improve the efficiency of arithmetic operations in digital systems? - The FA circuit enhances efficiency by generating sum and carry outputs accurately and quickly, improving overall performance in arithmetic calculations.

2. What are the key differences between a static CMOS based full adder circuit and other types of adder circuits? - Static CMOS based full adder circuits offer low power consumption and high noise immunity compared to other adder circuit designs.

Original Abstract Submitted

Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.