SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION

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SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18120838 titled 'SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION

Simplified Explanation: The patent application discusses the use of duty-cycle calibration to improve the performance of a phase-locked loop (PLL) by addressing duty cycle errors caused by higher reference clock frequencies.

Key Features and Innovation:

Introduction of a duty cycle calibration loop to address duty cycle errors in PLLs.
Utilization of frequency doublers to increase PLL reference clock frequency.
Incorporation of a static phase offset at the PLL input to improve low phase noise PLL architectures.
Extraction of phase offset information for duty cycle error detection and correction.

Potential Applications: The technology can be applied in various systems requiring precise clock synchronization, such as communication systems, data processing units, and instrumentation devices.

Problems Solved: The technology addresses duty cycle errors caused by higher reference clock frequencies, static phase offsets, and variations in phase noise, leading to improved PLL performance and accuracy.

Benefits:

Enhanced PLL performance with reduced phase noise.
Increased power efficiency.
Improved accuracy in duty cycle error detection and correction.
Minimized disturbances at the PLL output.

Commercial Applications: The technology can be utilized in telecommunications equipment, networking devices, test and measurement instruments, and other electronic systems requiring stable and accurate clock signals.

Prior Art: Readers interested in exploring prior art related to PLL duty-cycle calibration and phase noise reduction can refer to research papers, patents, and industry publications in the field of integrated circuit design and signal processing.

Frequently Updated Research: Researchers in the field of PLL design and clock synchronization continue to explore innovative techniques for improving phase-locked loop performance, reducing phase noise, and enhancing power efficiency in electronic systems.

Questions about PLL Duty-Cycle Calibration: 1. What are the key benefits of using duty-cycle calibration in PLLs? 2. How does the technology address duty cycle errors caused by higher reference clock frequencies?

Original Abstract Submitted

To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.