18109365. ELECTRONIC DEVICE FABRICATION USING AREA-SELECTIVE DEPOSITION simplified abstract (Applied Materials, Inc.)
ELECTRONIC DEVICE FABRICATION USING AREA-SELECTIVE DEPOSITION
Organization Name
Inventor(s)
Zachary J. Devereaux of Webberville MI (US)
Bhaskar Jyoti Bhuyan of Santa Clara CA (US)
Thomas Joseph Knisley of Livonia MI (US)
Zeqing Shen of San Jose CA (US)
Susmit Singha Roy of Campbell CA (US)
Mark J. Saly of Santa Clara CA (US)
Abhijit Basu Mallick of Fremont CA (US)
ELECTRONIC DEVICE FABRICATION USING AREA-SELECTIVE DEPOSITION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18109365 titled 'ELECTRONIC DEVICE FABRICATION USING AREA-SELECTIVE DEPOSITION
The method described in the abstract involves selectively forming passivation and catalyst layers to induce the formation of a supplemental dielectric layer with a low dielectric constant.
- Passivation layer is selectively formed on a first conductive layer in a first interlevel dielectric (ILD) layer.
- Catalyst layer is selectively formed on the passivation layer to induce the formation of a supplemental dielectric layer.
- Supplemental dielectric layer has a dielectric constant of less than or equal to about 4.
- Passivation layer prevents the catalyst layer from forming directly on the first conductive layer.
- Catalyst layer plays a key role in the formation of the supplemental dielectric layer.
Potential Applications: - Semiconductor manufacturing - Integrated circuit fabrication - Advanced electronic devices
Problems Solved: - Enhancing dielectric properties of interlevel dielectric layers - Improving performance and efficiency of electronic components
Benefits: - Lower dielectric constant for improved signal transmission - Enhanced reliability and durability of electronic devices - Increased efficiency in semiconductor manufacturing processes
Commercial Applications: Title: Advanced Dielectric Layer Formation Technology for Semiconductor Devices This technology can be utilized in the production of high-performance electronic devices, leading to faster and more reliable products in various industries such as telecommunications, computing, and consumer electronics.
Questions about Dielectric Layer Formation: 1. How does the catalyst layer influence the formation of the supplemental dielectric layer? 2. What are the specific advantages of using a dielectric material with a low dielectric constant in electronic devices?
Original Abstract Submitted
A method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer, selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer, and selectively forming at least one supplemental dielectric layer using the at least one catalyst layer. The at least one catalyst layer induces formation of the at least one supplemental dielectric layer, and the at least one supplemental dielectric layer includes a dielectric material having a dielectric constant of less than or equal to about 4.
- Applied Materials, Inc.
- Zachary J. Devereaux of Webberville MI (US)
- Bhaskar Jyoti Bhuyan of Santa Clara CA (US)
- Thomas Joseph Knisley of Livonia MI (US)
- Zeqing Shen of San Jose CA (US)
- Susmit Singha Roy of Campbell CA (US)
- Mark J. Saly of Santa Clara CA (US)
- Abhijit Basu Mallick of Fremont CA (US)
- H01L21/768
- C23C16/04
- C23C16/32
- C23C16/40
- C23C16/455
- H01L21/02
- CPC H01L21/76897