18059952. CAPACITOR AND FABRICATING METHOD THEREOF simplified abstract (NANYA TECHNOLOGY CORPORATION)
CAPACITOR AND FABRICATING METHOD THEREOF
Organization Name
Inventor(s)
Chih-Hsiung Huang of Kaohsiung City (TW)
Ning-Shuang Hsu of Chiayi City (TW)
CAPACITOR AND FABRICATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18059952 titled 'CAPACITOR AND FABRICATING METHOD THEREOF
Simplified Explanation
The abstract describes a capacitor for a memory device with a unique structure involving multiple layers of titanium nitride and silicon nitride.
- The bottom electrode of the capacitor consists of a first layer with a cup shape made of alternating titanium nitride and silicon nitride layers, and a second layer made of titanium nitride.
- The dielectric layer covers the internal surface of the second bottom electrode layer.
- The top electrode covers the dielectric layer.
Potential Applications
This technology can be applied in memory devices, such as DRAM or flash memory, to improve performance and efficiency.
Problems Solved
This innovation solves the problem of improving the capacitance and reliability of memory devices by utilizing a unique bottom electrode structure.
Benefits
The benefits of this technology include increased capacitance, improved reliability, and potentially lower power consumption in memory devices.
Potential Commercial Applications
- "Innovative Capacitor Design for Memory Devices: Improving Performance and Efficiency"
Possible Prior Art
There may be prior art related to capacitor structures in memory devices, but specific examples are not provided in the abstract.
Unanswered Questions
How does this capacitor structure compare to traditional capacitor designs in terms of performance and reliability?
The abstract does not provide a direct comparison between this capacitor structure and traditional designs, so it is unclear how they differ in terms of performance and reliability.
What manufacturing processes are required to produce this unique capacitor structure?
The abstract does not detail the specific manufacturing processes needed to produce this capacitor structure, leaving a gap in understanding the practical implementation of this technology.
Original Abstract Submitted
A capacitor for a memory device includes a substrate, a bottom electrode, a dielectric layer, and a top electrode. The bottom electrode includes a first bottom electrode layer and a second bottom electrode layer. The first bottom electrode layer is disposed on the substrate. The first bottom electrode layer has a cup shape. The first bottom electrode layer includes a plurality of titanium nitride layers and a plurality of silicon nitride layers that are stacked alternately. The second bottom electrode layer has a cup shape. The second bottom electrode layer includes titanium nitride. An external surface of the second bottom electrode layer contacts an internal surface of the first bottom electrode layer. The dielectric layer conformally covers an internal surface of the second bottom electrode layer. A top electrode conformally covers the dielectric layer.
