18059492. SEMICONDUCTOR MEMORY DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR MEMORY DEVICES
Organization Name
Inventor(s)
Euichul Jeong of Yongin-si (KR)
Kiseok Lee of Hwaseong-si (KR)
Hyungeun Choi of Suwon-si (KR)
SEMICONDUCTOR MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18059492 titled 'SEMICONDUCTOR MEMORY DEVICES
Simplified Explanation
The patent application describes a semiconductor memory device with a specific structure and configuration. Here are the key points:
- The device includes a transistor body with a first source/drain region, a single-crystal channel layer, and a second source/drain region arranged horizontally.
- A gate electrode layer extends in a perpendicular direction and covers the upper and lower surfaces of the single-crystal channel layer.
- A bit line is connected to the first source/drain region, extends vertically, and has a narrower width compared to the gate electrode layer.
- A spacer covers the upper and lower surfaces of the first source/drain region and has a wider width than the bit line.
- A cell capacitor is located on the opposite side of the transistor body from the bit line and consists of lower and upper electrode layers with a capacitor dielectric layer in between.
Potential applications of this technology:
- Memory devices: The semiconductor memory device described in the patent application can be used in various memory applications, such as computer systems, smartphones, and other electronic devices.
Problems solved by this technology:
- Improved performance: The specific structure and configuration of the semiconductor memory device can enhance its performance, including speed and reliability.
Benefits of this technology:
- Higher memory density: The described device allows for a higher memory density due to its compact structure and efficient use of space.
- Enhanced performance: The specific configuration of the device can improve its overall performance, leading to faster and more reliable memory operations.
Original Abstract Submitted
A semiconductor memory device including a transistor body extending in a first horizontal direction and including a first source/drain region, a single-crystal channel layer, and a second source/drain region sequentially arranged in the first horizontal direction, a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering upper and lower surfaces of the single-crystal channel layer, a bit line connected to the first source/drain region, extending in a vertical direction, and having a first width in the second horizontal direction, a spacer covering upper and lower surfaces of the first source/drain region and having a second width greater than the first width, and a cell capacitor on a side opposite to the bit line with respect to the transistor body in the first horizontal direction and including lower and upper electrode layers and a capacitor dielectric layer therebetween may be provided.
