ERROR PROTECTION FOR MANAGED MEMORY DEVICES

Organization Name

Micron Technology, Inc.

Inventor(s)

Chandrakanth Rapalli of Hyderabad (IN)

Yoav Weinberg of Toronto (CA)

Tal Sharifie of Lehavim (IL)

ERROR PROTECTION FOR MANAGED MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18048284 titled 'ERROR PROTECTION FOR MANAGED MEMORY DEVICES

Simplified Explanation

The patent application describes methods, systems, and devices for error protection in managed memory devices. The memory system receives data units from a host device, performs error detection operations, generates protocol units with different sets of parity bits, and stores the data units with additional parity bits in a memory device.

Memory system receives data units from host device
Error detection operations are performed on the data units
Protocol units are generated with different sets of parity bits
Data units are stored with additional parity bits in a memory device

Key Features and Innovation

Error protection for managed memory devices
Generation of protocol units with different sets of parity bits
Storage of data units with additional parity bits in memory devices

Potential Applications

This technology can be applied in various memory systems, data storage devices, and communication systems where error protection is crucial.

Problems Solved

Ensures data integrity in managed memory devices
Reduces the risk of data corruption during storage and transmission

Benefits

Improved reliability of memory systems
Enhanced data integrity and security
Reduced data loss and corruption risks

Commercial Applications

Potential commercial applications include data centers, cloud storage services, IoT devices, and communication networks where data integrity is essential for operations and security.

Prior Art

Information on prior art related to this technology is not provided in the abstract.

Frequently Updated Research

There is no information on frequently updated research relevant to this technology.

Questions about Error Protection for Managed Memory Devices

Question 1

How does the memory system ensure data integrity in managed memory devices?

The memory system ensures data integrity by performing error detection operations on data units, generating protocol units with different sets of parity bits, and storing data units with additional parity bits in memory devices.

Question 2

What are the potential commercial applications of this technology?

Potential commercial applications include data centers, cloud storage services, IoT devices, and communication networks where data integrity is crucial for operations and security.

Original Abstract Submitted

Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

18048284. ERROR PROTECTION FOR MANAGED MEMORY DEVICES simplified abstract (Micron Technology, Inc.)