COMMAND AND DATA PATH ERROR PROTECTION

Organization Name

Micron Technology, Inc.

Inventor(s)

Chandrakanth Rapalli of Hyderabad (IN)

Yoav Weinberg of Toronto (CA)

Tal Sharifie of Lehavim (IL)

COMMAND AND DATA PATH ERROR PROTECTION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18048283 titled 'COMMAND AND DATA PATH ERROR PROTECTION

Simplified Explanation

The patent application describes methods, systems, and devices for error protection in command and data paths within a memory system.

The memory system receives data units from a host device, which include sets of parity bits for error detection.
A protocol unit is generated using a subset of data from the data units, including a different set of parity bits for error detection.
A data storage unit is then created using data from the protocol unit, along with another set of parity bits, and stored in a memory device.

Key Features and Innovation

Error protection in command and data paths within a memory system.
Use of different sets of parity bits for error detection in data units and protocol units.
Storage of data units and parity bits in a memory device for enhanced error protection.

Potential Applications

The technology can be applied in various memory systems, data storage devices, and communication systems where error protection is crucial.

Problems Solved

Enhanced error detection and protection in memory systems.
Improved reliability of data transmission and storage.
Minimization of data corruption and loss.

Benefits

Increased data integrity and reliability.
Reduced risk of data loss and corruption.
Enhanced performance of memory systems.

Commercial Applications

The technology can be utilized in data centers, servers, networking equipment, and other devices where data integrity and error protection are essential for optimal performance and reliability.

Prior Art

There may be existing patents or technologies related to error protection in memory systems, but the specific approach described in this patent application may offer unique advantages and improvements.

Frequently Updated Research

There may be ongoing research in the field of error protection in memory systems, data storage, and communication technologies that could further enhance the capabilities and applications of this innovation.

Questions about Error Protection in Memory Systems

Question 1

How does the use of different sets of parity bits in data units and protocol units improve error detection in memory systems?

The use of different sets of parity bits allows for more robust error detection by introducing redundancy and diversity in error checking mechanisms, enhancing the overall reliability of data transmission and storage.

Question 2

What are the potential challenges in implementing error protection mechanisms in memory systems, and how does this technology address them?

Implementing error protection mechanisms in memory systems can be complex and resource-intensive. This technology addresses these challenges by providing a systematic approach to error detection and protection, optimizing the use of resources while maximizing data integrity and reliability.

Original Abstract Submitted

Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.