18034832. PARALLELIZED DECODING OF VARIABLE-LENGTH PREFIX CODES simplified abstract (Microsoft Technology Licensing, LLC)

PARALLELIZED DECODING OF VARIABLE-LENGTH PREFIX CODES

Organization Name

Microsoft Technology Licensing, LLC

Inventor(s)

Daniel Lo of Bothell WA (US)

Blake D. Pelton of Redmond WA (US)

PARALLELIZED DECODING OF VARIABLE-LENGTH PREFIX CODES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18034832 titled 'PARALLELIZED DECODING OF VARIABLE-LENGTH PREFIX CODES

Simplified Explanation

The patent application describes methods and systems for decoding variable-length codes in a parallel process. Here are the key points:

• Variable-length code words are divided into fixed length words.
• Multiple sets of decoder circuits work in parallel, each receiving a current fixed length word and a prior fixed length word.
• Each decoder circuit has a fixed leftover bit-count and generates an output that includes a decoded symbol and a new leftover bit-count.
• The output of each decoder circuit is determined based on the current fixed length word, the prior fixed length word, and the fixed leftover bit-count.
• Selected decoder circuit outputs are generated based on a set of first leftover bit-counts.
• A final output is selected from each set of selected decoder circuit outputs based on a second prior leftover bit-count.

Potential applications of this technology:

• Data compression: Variable-length codes are commonly used in data compression algorithms, and this technology can improve the efficiency and speed of decoding these codes.
• Communication systems: Variable-length codes are used in various communication protocols, and this technology can enhance the decoding process in these systems.
• Image and video processing: Variable-length codes are often used in image and video compression techniques, and this technology can optimize the decoding of these codes.

Problems solved by this technology:

• Efficient decoding: Variable-length codes can be challenging to decode due to their variable lengths, and this technology provides a parallel process that improves the speed and efficiency of decoding.
• Error correction: The use of multiple decoder circuits and the selection of the final output based on prior leftover bit-counts can help in error correction and improve the accuracy of decoding.

Benefits of this technology:

• Faster decoding: By dividing the variable-length codes into fixed length words and using parallel decoder circuits, the decoding process can be significantly accelerated.
• Improved efficiency: The selection of decoder circuit outputs based on leftover bit-counts allows for more accurate decoding and reduces the need for additional processing steps.
• Enhanced error correction: The use of multiple decoder circuits and the selection of the final output based on prior leftover bit-counts can help in error correction and improve the overall reliability of the decoding process.

Original Abstract Submitted

Methods and systems are provided for decoding variable-length codes in a parallel process. A stream of variable-length code words is divided into fixed length words. A plurality of parallel sets of decoder circuits each receive, in parallel, a current fixed length word and a prior fixed length word. Each decoder circuit has a respective fixed leftover bit-count. Each decoder circuit generates a respective output that may include a decoded symbol and a new leftover bit-count. Each respective output is determined based on the respective current fixed length word, the respective prior fixed length word, and the respective fixed leftover bit-count. A set of selected decoder circuit outputs is generated for each set of the parallel sets of decoder circuits based on a set of first leftover bit-counts. One output from each set of selected decoder circuit outputs is selected as a final output based on a second prior leftover bit-count.