17958386. NONVOLATILE MEMORY DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
NONVOLATILE MEMORY DEVICES
Organization Name
Inventor(s)
Hee-Woong Kang of Suwon-si (KR)
Dong-Hun Kwak of Hwaseong-si (KR)
Jun-Ho Seo of Hwaseong-si (KR)
NONVOLATILE MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17958386 titled 'NONVOLATILE MEMORY DEVICES
Simplified Explanation
The abstract describes a nonvolatile memory device that includes a memory cell array and a row decoder. The memory cell array consists of multiple mats, each containing cell strings connected to word-lines, bit-lines, and string selection lines. The row decoder applies different voltages to the word-lines based on the operating mode of the device.
- The memory device has a memory cell array with multiple mats.
- Each mat has cell strings connected to word-lines, bit-lines, and string selection lines.
- The row decoder applies different voltages to the word-lines.
- In single mat mode, a specific voltage is applied to a word-line for a certain period of time.
- In multi-mat mode, a different voltage is applied to the same word-line for a longer period of time.
Potential applications of this technology:
- Nonvolatile memory devices, such as flash memory or solid-state drives.
- Electronic devices that require data storage, such as smartphones, tablets, or laptops.
- Industrial applications that require reliable and high-capacity memory storage.
Problems solved by this technology:
- Efficient operation of nonvolatile memory devices with multiple mats.
- Proper voltage control for different operating modes.
- Ensuring reliable and accurate data storage and retrieval.
Benefits of this technology:
- Improved performance and efficiency of nonvolatile memory devices.
- Enhanced reliability and durability of data storage.
- Simplified design and operation of memory cell arrays.
- Increased capacity and speed of data storage and retrieval.
Original Abstract Submitted
A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.
