17957820. DIRECTED REFRESH MANAGEMENT FOR DRAM simplified abstract (ADVANCED MICRO DEVICES, INC.)
DIRECTED REFRESH MANAGEMENT FOR DRAM
Organization Name
Inventor(s)
Kevin M. Brandl of Austin TX (US)
James R. Magro of Lakeway TX (US)
Kedarnath Balakrishnan of Bangalore (IN)
DIRECTED REFRESH MANAGEMENT FOR DRAM - A simplified explanation of the abstract
This abstract first appeared for US patent application 17957820 titled 'DIRECTED REFRESH MANAGEMENT FOR DRAM
Simplified Explanation
The memory controller described in the patent application includes a row hammer logic circuit that generates a sample request. Upon receiving the sample request, the memory controller sends a sample command to the memory, causing it to capture a current row. Once the sample command is completed, the memory controller sends a mitigation command to the memory.
- Row hammer logic circuit generates sample request
- Memory controller sends sample command to memory
- Memory captures current row in response to sample command
- Memory controller sends mitigation command after sample command completion
Potential Applications
This technology could be applied in various memory systems where row hammering is a concern, such as in high-performance computing, data centers, and gaming consoles.
Problems Solved
1. Preventing row hammering in memory systems 2. Enhancing memory reliability and performance
Benefits
1. Improved memory system stability 2. Increased memory access speed 3. Enhanced overall system performance
Potential Commercial Applications
Optimizing memory controllers in servers for improved data processing speed and reliability.
Possible Prior Art
One possible prior art is the use of ECC (Error-Correcting Code) memory modules to detect and correct memory errors, but this does not specifically address the issue of row hammering.
Unanswered Questions
How does the row hammer logic circuit determine when to generate a sample request?
The patent application does not provide details on the specific criteria or triggers for the row hammer logic circuit to initiate a sample request.
What impact does the mitigation command have on the memory system's operation?
The patent application does not elaborate on the specific actions or changes implemented by the mitigation command in the memory system.
Original Abstract Submitted
A memory controller for generating accesses for a memory includes a row hammer logic circuit for providing a sample request. In response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row. In response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory.