17888325. CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE
Organization Name
Inventor(s)
Jonathan S. Parry of Boise ID (US)
Nitul Gohain of Bangalore (IN)
CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17888325 titled 'CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE
Simplified Explanation
Methods, systems, and devices for caching for a multiple-level memory device are described in the patent application. The abstract explains the process of receiving data, writing it to multiple-level cells using different programming modes, transferring data between cells, and making determinations on how to write new data based on available cells.
- Data is received for writing to a memory device with multiple-level cells.
- The data is first written to first multiple-level cells using a first programming mode.
- The data is then transferred from the first cells to second cells using a third programming mode.
- Later, second data is received for writing to the memory device.
- A determination is made on whether to write the second data to third cells using the first programming mode or a second programming mode based on available cells ready for programming.
Potential Applications
- Data storage devices
- Computer memory systems
- Mobile devices
Problems Solved
- Efficient use of multiple-level memory cells
- Optimal programming modes for data writing
- Improved data transfer between cells
Benefits
- Enhanced data storage capabilities
- Increased efficiency in memory device operations
- Improved performance and reliability of memory systems
Original Abstract Submitted
Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
