17885364. Absolute Difference Circuitry with Parallel Comparison Logic simplified abstract (Apple Inc.)
Absolute Difference Circuitry with Parallel Comparison Logic
Organization Name
Inventor(s)
Michael L. Liu of Palo Alto CA (US)
Yash H. Malviya of San Jose CA (US)
Absolute Difference Circuitry with Parallel Comparison Logic - A simplified explanation of the abstract
This abstract first appeared for US patent application 17885364 titled 'Absolute Difference Circuitry with Parallel Comparison Logic
Simplified Explanation
The abstract describes an integrated circuit with absolute difference circuitry that computes an absolute difference value using comparison logic, an adder, and a multiplexer.
- Comparison logic compares two input values and generates a comparison value based on their relationship.
- The adder calculates the sum of the first input value, an inverted version of the second input value, and the comparison value.
- The multiplexer selects either the sum or the inverted sum based on the comparison value to output the absolute difference value.
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- Potential Applications
- Signal processing applications
- Image processing applications
- Data compression algorithms
- Problems Solved
- Efficient computation of absolute differences
- Simplified circuit design for computing absolute differences
- Benefits
- Faster computation of absolute differences
- Reduced circuit complexity
- Improved performance in various applications
Original Abstract Submitted
An integrated circuit can include absolute difference circuitry configured to compute an absolute difference value. The absolute difference circuitry may include a comparison logic, a single adder, and a multiplexer. The comparison logic may receive a first input value and a second input value and may generate a comparison value based on whether the first input value exceeds the second input value. The adder may compute a sum of the first input value, an inverted version of the second input value, and the comparison value. The multiplexer may receive the sum and an inverted version of the sum and may output either the sum or the inverted version of the sum based on the comparison value to produce the absolute difference value.
