17547413. OPTIMIZATION OF ARITHMETIC EXPRESSIONS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
OPTIMIZATION OF ARITHMETIC EXPRESSIONS
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
MIHIR Choudhury of Jersey City NJ (US)
Ayesha Akhter of Austin TX (US)
Robert Lowell Kanzelman of Rochester MN (US)
OPTIMIZATION OF ARITHMETIC EXPRESSIONS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17547413 titled 'OPTIMIZATION OF ARITHMETIC EXPRESSIONS
Simplified Explanation
The patent application describes an approach for optimizing integer arithmetic expressions implemented as a Boolean logic circuit. Here are the key points:
- The processor converts arithmetic operators in an arithmetic expression into adders.
- The adders are identified and arranged in a topological order.
- The adders are then merged based on the topological order to create a multi-operand adder.
- The multi-operand adder is further converted into a compressor tree and a two-operand adder.
- The arithmetic expression is performed using the converted multi-operand adder.
Potential Applications:
- This technology can be applied in various fields that involve integer arithmetic operations, such as computer processors, digital signal processing, and cryptography.
- It can be used to optimize the performance and efficiency of arithmetic operations in these applications.
Problems Solved:
- Traditional approaches for implementing arithmetic expressions in Boolean logic circuits can be inefficient and result in complex circuit designs.
- This technology solves the problem of optimizing the circuit design by converting arithmetic operators into adders and merging them into a more efficient multi-operand adder.
Benefits:
- The optimized circuit design improves the performance and efficiency of arithmetic operations.
- It reduces the complexity of the circuit design, resulting in smaller and more cost-effective implementations.
- The approach can be applied to a wide range of arithmetic expressions and can be easily integrated into existing systems.
Original Abstract Submitted
In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.
