US Patent Application 17863000. MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM simplified abstract

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MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

Organization Name

Micron Technology, Inc.

Inventor(s)

Kishore Kumar Muchherla of Fremont CA (US)

Jonathan S. Parry of Boise ID (US)

Nicola Ciocchini of Boise ID (US)

Animesh Roy Chowdhury of Boise ID (US)

Akira Goda of Tokyo (JP)

Jung Sheng Hoei of Newark CA (US)

Niccolo' Righetti of Boise ID (US)

Ugo Russo of Boise ID (US)

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 17863000 titled 'MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

Simplified Explanation

- The patent application describes a system that includes a memory device and a processing device. - The processing device receives two read commands at different times for a set of memory cells in the memory device. - The processing device increments a read counter for the memory device based on the time difference between the two read commands. - The processing device determines if the value of the read counter meets a threshold criterion. - If the threshold criterion is satisfied, the processing device performs a data integrity scan on the set of memory cells.

  • Memory device with multiple memory cells and a processing device are part of the system.
  • Processing device receives two read commands at different times for a set of memory cells.
  • Read counter for the memory device is incremented based on the time difference between the read commands.
  • Processing device checks if the value of the read counter meets a threshold criterion.
  • If the threshold criterion is met, a data integrity scan is performed on the set of memory cells.


Original Abstract Submitted

A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.