Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on April 11th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on April 11th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 35 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (12), H01L27/092 (11), H01L29/775 (10), H01L29/423 (9), H01L23/00 (8)
With keywords such as: semiconductor, structure, layer, gate, substrate, forming, dielectric, portion, region, and source in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Chih-Hao YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo HSIA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng TAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chung YEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/122, G02B6/12, G02B6/13
Abstract: a photonic semiconductor device including a light-emitting component and a photonic integrated circuit is provided. the light-emitting component at least includes a gain medium layer, a first contact layer and a first optical coupling layer stacked to each other. the photonic integrated circuit includes a second optical coupling layer. the light-emitting component and the photonic integrated circuit are stacked in a stacking direction, the first optical coupling layer has a first taper portion, the second optical coupling layer has a second taper portion, and the first taper portion and the second taper portion overlap in the stacking direction. accordingly, the light emitted from the gain medium layer may be transmitted to the second taper portion from the first taper portion by optical coupling in a short length of an optical coupling path.
Inventor(s): Chun-Chih HO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Chang of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/075, H01L21/027
Abstract: a method of manufacturing a semiconductor device includes forming a first layer having an organic material over a substrate. a second layer is formed over the first layer, wherein the second layer includes a silicon-containing polymer having pendant acid groups or pendant photoacid generator groups. the forming a second layer includes: forming a layer of a composition including a silicon-based polymer and a material containing an acid group or photoacid generator group over the first layer, floating the material containing an acid group or photoacid generator group over the silicon-based polymer, and reacting the material containing an acid group or photoacid generator group with the silicon-based polymer to form an upper second layer including a silicon-based polymer having pendant acid groups or pendant photoacid generator groups overlying a lower second layer comprising the silicon-based polymer. a photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.
Inventor(s): Jian-Sing LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Wei CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/394, G06F30/392
Abstract: a method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. the method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. the method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. the method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.
Inventor(s): Hsi-Wen Tien of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hao Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Ren Dai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ju Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/768
Abstract: semiconductor device and the manufacturing method thereof are disclosed herein. an exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.
Inventor(s): Te-Chih HSIUNG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Hua CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Bing-Sian WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsuan CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Kuo HSIEH of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yuan TING of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Just LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/8238, H01L27/092, H01L29/08, H01L29/417, H01L29/66
Abstract: a method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ild) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ild layer; recessing the portion of the dielectric structure embedded in the ild layer; after recessing the portion of the dielectric structure, removing a portion of the ild layer over the source/drain epitaxial structure; and forming a source/drain contact in the ild layer and in contact with the portion of the dielectric structure.
Inventor(s): Lung-Kai Mao of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsiung Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Wei Lee of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Hsien Lee of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Ning Feng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3065, H01L21/311, H01L23/00, H01L23/13, H01L23/14
Abstract: a semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. the semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration. the second substrate has a second width along the horizontal direction, where the second width is greater than the first width
Inventor(s): Tai-Jung Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Cheng Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wan Chen Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhen-Cheng Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hui Lin of Dajia Township (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/02, H01L21/8234, H01L27/088
Abstract: a method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. the process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.
Inventor(s): Cheng-Wei CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu CHOU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Lun-Kuang TAN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L29/06, H01L29/423, H01L29/66
Abstract: a method for modulating a threshold voltage of a device. the method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a p-type transistor. in some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the p-type transistor. thereafter, the method further includes forming a p-type metal film surrounding the first gate dielectric layer. in an example, and after forming the p-type metal film, the method further includes annealing the semiconductor device. after the annealing, and in some embodiments, the method includes removing the p-type metal film.
Inventor(s): Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Gang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/00, H01L23/528
Abstract: an integrated circuit (ic) device includes a substrate. the ic device includes a multi-layer interconnect structure disposed over a first side of the substrate. the multi-layer interconnect structure includes a plurality of metal layers. the ic device includes a first portion of a through-substrate via (tsv) disposed over the first side of the substrate. the first portion of the tsv includes a plurality of conductive components belonging to the plurality of metal layers of the multi-layer interconnect structure. the ic device includes a second portion of the tsv that extends vertically through the substrate from the first side to a second side opposite the first side. the second portion of the tsv is electrically coupled to the first portion of the tsv.
Inventor(s): Wei-Hao LIAO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Hsi-Wen TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Hsu WU of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei SU of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/3065, H01L21/768, H01L29/66
Abstract: embodiments of the present disclosure relates to a method for forming a semiconductor device structure. the method includes including forming one or more conductive features in a first interlayer dielectric (ild), forming an etch stop layer on the first ild, forming a second ild over the etch stop layer, forming one or more openings through the second ild and the etch stop layer to expose a top surface of the one or more first conductive features, wherein the one or more openings are formed by a first etch process in a first process chamber, exposing the one or more openings to a second etch process in a second process chamber so that the shape of the or more openings is elongated, and filling the one or more openings with a conductive material.
Inventor(s): Yi-Bo LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jin CAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H10B10/00
Abstract: a device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent the first stack; a first gate structure wrapping around the first stack and the second stack; a second gate structure wrapping around the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and a via. the via includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.
20240120277.CHIP STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Hong-Seng SHUE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Han TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chin CHANG of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Mirng-Ji LII of Sinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching HSU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/00, H01L23/522
Abstract: a chip structure is provided. the chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. the insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.
Inventor(s): Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Chun LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shyue-Ter LEU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/04, H01L23/10, H01L23/367
Abstract: a chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. the chip package includes a first and a second support structures below the thermal conductive structure. the first and the second support structures connect the substrate and corners of the thermal conductive structure. the thermal conductive structure has a side edge connecting the first and the second support structures. the first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. the first and the second support structures are disposed along a side of the substrate. the first support structure is laterally separated from the side of the substrate by a first lateral distance. the side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.
Inventor(s): Szu-Hsien Lee of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chung Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Wei Lee of Oingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Fu Wei Liu of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Jhao-Yi Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/3205, H01L23/00
Abstract: a semiconductor chip and a manufacturing method thereof are provided. the semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. active devices formed inside the semiconductor chip are electrically connected to the working pillar. the ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.
Inventor(s): Sheng-Yao YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ling-Wei LI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jui WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lin HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chen LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lieh-Chuan CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Jung CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chio LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768
Abstract: a chip package structure is provided. the chip package structure includes a chip. the chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. the conductive ring-like structure surrounds a central region of the chip. the chip package structure includes a first solder structure over the conductive ring-like structure. the first solder structure and the conductive ring-like structure are made of different materials.
Inventor(s): Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Cherng Sheu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Fong Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yun Chen Teng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Han-De Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/265, H01L21/683, H01L21/78, H01L25/00
Abstract: methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. in an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. the method also includes forming a back-side interconnect structure over a back side of the transistor structure.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Chiang Huang of Saratoga CA (US) for taiwan semiconductor manufacturing company, ltd., Yun-Han Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung Lu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/48, H01L23/538, H01L25/00, H01L25/18, H10B80/00
Abstract: a semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. the semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. the semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. the semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.
Inventor(s): Wei-Chih KAO of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Che CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Ya YEH of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming an isolation layer over a substrate. the method includes forming a spacer layer over the first fin, the second fin, and the isolation layer. the method includes forming a gate dielectric layer in the first trench and covering the first fin, the second fin, and the isolation layer exposed by the first trench. the method includes partially removing the gate dielectric layer to form a second trench in the gate dielectric layer and between the first fin and the second fin. the method includes forming a gate electrode in the first trench of the spacer layer and over the gate dielectric layer.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hung HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chiang HONG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wing YEUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua PAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsuan LU of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238
Abstract: a semiconductor device structure is provided. the semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. a second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. a contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. the first electric wall has a gradually decreasing width wtowards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.
Inventor(s): Ming-Chyi LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiech-Fun LU of Taiwan (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang LIU of Alian Township (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Liang LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: a self-aligned plug may be formed between deep trench isolation (dti) etching cycles. accordingly, etch depth in areas of a pixel sensor with large cds (e.g., at an x-road) is reduced, which prevents trench loading. as a result, a floating diffusion (fd) region, associated with photodiodes of the pixel sensor, is not damaged during the dti etching cycles. reduced chances of damage to the fd region improves performance of the pixel sensor and prevents electrical shorts and failures, which increases yield and conserves time and raw materials used in forming the pixel sensor.
Inventor(s): Po Shao Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Ming Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., You-Ting Lin of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Yu Mei Jian of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66, H01L29/786
Abstract: semiconductor structures and methods are provided. a semiconductor structure according to the present disclosure includes a first active region extending lengthwise along a first direction and having a first width along a second direction perpendicular to the first direction, a second active region extending lengthwise along the first direction and having a second width along the second direction, and an epitaxial feature sandwiched between the first active region and the second active region along the first direction. the first width is greater than the second width.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/66, H01L29/775, H01L29/786
Abstract: semiconductor structures and processes are provided that include a first gate isolation structure and a second gate isolation structure. the first gate isolation structure may be formed on a dielectric wall from which nanostructure channel regions extend. the second gate isolation structure may be formed on a shallow trench isolation feature. the height of the first gate isolation structure is less than the height of the second gate isolation structure. the composition of the first gate isolation structure may be different than the composition of the second gate isolation structure. in some implementations, the first gate isolation structure is formed concurrently with gate spacers.
Inventor(s): Ding-Kang SHIH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/285, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/45, H01L29/66, H01L29/775
Abstract: a semiconductor device includes a channel structure including a plurality of channel features which are spaced apart from each other, and which include first semiconductor elements, and two source/drain features disposed at two opposite sides of the channel structure such that each of the channel features interconnects the source/drain features. a major portion of each of the source/drain features includes second semiconductor elements, stressor elements which have an atomic radius different from that of the second semiconductor elements, and which are present in an amount sufficient to permit the source/drain features to apply a first stress to the channel features, and a certain degree of lattice defects present such that the source/drain features including the stressor elements apply a second stress to the channel features. the second stress is opposite to the first stress. a method for manufacturing the semiconductor device is also disclosed.
Inventor(s): Li-Wei Yin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Wen Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsien Lin of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Jih-Sheng Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh Chao of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chia Ming Liang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yih-Ann Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/3213, H01L29/423
Abstract: provided are structures and methods for forming structures with sloping surfaces of a desired profile. an exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.
Inventor(s): Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L27/092, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775
Abstract: embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. the structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. the second portion is disposed in the dielectric material. the structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. the conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.
Inventor(s): Tzu-Ging Lin of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Shun-Hui Yang of Jungli (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/786
Abstract: provided are multi-gate devices and methods for fabricating such devices. an exemplary method includes forming gate structures over a semiconductor material, wherein the gate structures include a long channel (lc) gate structure and a short channel (sc) gate structure; forming a patterned mask over the semiconductor material, wherein the lc gate structure and the sc gate structure are not covered by the patterned mask; and performing an etch process on the lc gate structure and on the sc gate structure through the patterned mask to remove the lc gate structure and the sc gate structure, wherein removal of the lc gate structure forms a deep trench in the semiconductor substrate having a first depth, and wherein removal of the sc gate structure forms a shallow trench in the semiconductor substrate having a second depth less than the first depth.
Inventor(s): Jia-Ni YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Lin HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun CHU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/66
Abstract: a semiconductor device structure, along with methods of forming such, are described. the semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
Inventor(s): Miin-Jang Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuen-Yu Tsai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/308
Abstract: a method for forming a semiconductor device is provided. a first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. a second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. the combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hung HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/08, H01L29/423, H01L29/66
Abstract: embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. the structure includes a semiconductor layer disposed over a substrate, and the semiconductor layer has a first end and a second end opposite the first end. the structure further includes an epitaxial feature disposed over the substrate, and the epitaxial feature is electrically connected to the first end of the semiconductor layer. the structure further includes a first dielectric layer disposed over the substrate, and the first dielectric layer is in contact with the second end of the semiconductor layer. the structure further includes a contact etch stop layer disposed on and in contact with the first dielectric layer and an interlayer dielectric layer disposed on and in contact with the contact etch stop layer.
Inventor(s): Po-Hsiang Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsui-Ping Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Shin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01Q1/22, H01L23/66, H01Q1/50, H01Q23/00
Abstract: a 3d ic package is provided. the 3d ic package includes: a first ic die comprising a first substrate at a back side of the first ic die; a second ic die stacked at the back side of the first ic die and facing the first substrate; a tsv through the first substrate and electrically connecting the first ic die and the second ic die, the tsv having a tsv cell including a tsv cell boundary surrounding the tsv; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the tsv, and the protection module is within the tsv cell.
Inventor(s): Chia-Lin HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fu TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ti SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ji CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02H9/04, H01L27/02, H02H1/00
Abstract: an electrostatic discharge (esd) circuit includes a first esd detection circuit, a first discharging circuit and a first esd assist circuit. the first esd detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. the first discharging circuit includes a first transistor. the first transistor has a first gate, a first drain, a first source and a first body terminal. the first gate is coupled to the first esd detection circuit by a third node. the first drain is coupled to the first node. the first source and the first body terminal are coupled together at the second node. the first esd assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an esd event at the first or second node.
Inventor(s): Y.L. Cheng of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Wen Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsien Lin of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
Abstract: methods for fabricating semiconductor structures are provided. an exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. the method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. the method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mtorr).
Inventor(s): Georgios Vellianitis of Heverlee (BE) for taiwan semiconductor manufacturing company, ltd., Gerben Doornbos of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L21/28, H01L23/522, H01L29/417, H01L29/66, H01L29/78, H10B51/10
Abstract: ferroelectric field effect transistors are in a three-dimensional structure that includes vertical columns. source/drain electrodes are provided by horizontal conductive layers that are interleaved with dielectric layers. channels for the fefets in each vertical column are provided by a continuous semiconductor layer, e.g., a vertical strip of semiconductor. another vertical strip may provide the ferroelectric layers for the fefets in the vertical column. the gate electrodes are provided by a control gate structure that connects the gate electrodes in parallel. the source/drain electrodes of multiple vertical columns may be connected in parallel. the source/drain electrodes of multiple tiers may also be connected in parallel. this structure provides high area density, adds an extra degree of freedom in circuit design, and lends itself to the use of oxide semiconductor channels.
Inventor(s): Joung-Wei Liou of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chin Kun Lan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01
Abstract: an mram cell has a bottom electrode, a metal tunneling junction, and a top electrode. the metal tunneling junction has a side surface between the bottom electrode and the top electrode. a thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. the thin layer has a lower conductance than the mtj. the electrode metal may have been deposited on the side during mtj patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. the thin layer may include an oxide deposited over the redeposited electrode metal. the thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. a silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on April 11th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G02B6/122
- G02B6/12
- G02B6/13
- Taiwan semiconductor manufacturing company, ltd.
- G03F7/075
- H01L21/027
- G06F30/394
- G06F30/392
- H01L21/033
- H01L21/768
- H01L21/28
- H01L21/8238
- H01L27/092
- H01L29/08
- H01L29/417
- H01L29/66
- H01L21/3065
- H01L21/311
- H01L23/00
- H01L23/13
- H01L23/14
- H01L21/762
- H01L21/02
- H01L21/8234
- H01L27/088
- H01L29/06
- H01L29/423
- H01L23/48
- H01L23/528
- H01L23/522
- H10B10/00
- H01L23/04
- H01L23/10
- H01L23/367
- H01L23/58
- H01L21/3205
- H01L21/265
- H01L21/683
- H01L21/78
- H01L25/00
- H01L25/065
- H01L23/31
- H01L23/538
- H01L25/18
- H10B80/00
- H01L29/775
- H01L27/146
- H01L29/786
- H01L21/285
- H01L29/45
- H01L29/40
- H01L21/3213
- H01L21/308
- H01Q1/22
- H01L23/66
- H01Q1/50
- H01Q23/00
- H02H9/04
- H01L27/02
- H02H1/00
- H10B51/20
- H01L29/78
- H10B51/10
- H10N50/80
- H10B61/00
- H10N50/01
