Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on January 25th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on January 25th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 52 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (14), H01L29/423 (11), H01L29/78 (10), H01L29/06 (10), H01L29/42392 (9)
With keywords such as: layer, structure, semiconductor, gate, device, substrate, source, drain, layers, and channel in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Hsien Hua SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsun-Chung KUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B24B53/017, B24B53/12
Abstract: a pad conditioner for conditioning a polishing surface of a polishing pad includes a conditioning disk, a disk holder, and a disk arm. the conditioning disk includes a substrate plate and at least two abrasive segments. the conditioning disk includes at least one channel by which debris and spent slurry may be evacuated. the abrasive segments are on a surface of the substrate plate, and form at least one channel segment therebetween. each channel segment extends from about the center of the surface to substantially the outer rim of the substrate plate. the disk holder to which the conditioning disk is mounted includes a through hole. the disk arm to which the conditioning disk is mounted includes an opening in fluid communication with the at least one channel segment via the through hole for evacuating the debris and spent slurry by a vacuum module.
Inventor(s): En-Tian LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chiao-Ling WENG of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N31/22, G01N33/18
Abstract: a method for determining the concentration of a compound in ultrapure water is provided. the method includes dividing the ultrapure water into a first part and a second part and decomposing the compound in the first part, so that the first part includes a characteristic substance. the method also includes measuring a first concentration of the characteristic substance in the first part and a second concentration of the characteristic substance in the second part and calculating the difference between the first concentration and the second concentration. the method further includes obtaining the concentration of the compound in the ultrapure water based on the difference.
Inventor(s): Chia-Hong Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ting Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Mill-Jer Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01R31/265
Abstract: a method includes: providing a first semiconductor device including a backside interconnection structure, the first semiconductor device being formed by a semiconductor process; and generating a physical failure analysis model by an inspection process. the inspection process includes: directing an electron beam toward the frontside of the first semiconductor device; and applying an electrical signal to an electrical contact of the first semiconductor device through an electrical path that goes through a shunt board attached to a switchable interface trace bank, the electrical contact being associated with a position of the electron beam. the method further includes: generating a parameter of a revised semiconductor process according to the physical failure analysis model and the semiconductor process; and forming a second semiconductor device by the revised semiconductor process using the parameter.
Inventor(s): Jonathan Tsung-Yung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jen LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yih WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Haruki MORI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F3/06, G11C11/419, G11C7/10, G11C8/16, G06N3/063
Abstract: a charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for cim computing. in some embodiments, a capacitor is associated with each sram cell, and the capacitors associated with all sram cells in a column are included in averaging the rbl current. in some embodiments, a memory unit associated to an rbl in a cim device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. the memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. the memory unit further include a second switch device adapted to transfer the charge on the capacitor to the rbl.
Inventor(s): Hiroki NOGUCHI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Der CHIH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsueh-Chih YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Randy OSBORNE of Beaverton OR (US) for taiwan semiconductor manufacturing co., ltd., Win San KHWA of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F11/10, G11C11/16, G11C29/52
Abstract: a memory device, such as a mram device, includes a plurality of memory macros, where each includes an array of memory cells and a first ecc circuit configured to detect data errors in the respective memory macro. a second ecc circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. the second ecc circuit is configured to receive the detected data errors from the first ecc circuits of the plurality of memory macros and correct the data errors.
Inventor(s): Yu-Tao Yang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Shen Chou of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chow Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Hsu Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/392, G06F11/32, G06F30/398
Abstract: techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. the techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.
Inventor(s): Xiaoyu Sun of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Rawan Naous of Pleasanton (LB) for taiwan semiconductor manufacturing co., ltd., Murat Kerem Akarvardar of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06N3/04
Abstract: a reconfigurable processing circuit of an ai accelerator and a method of operating the same are disclosed. in one aspect, the reconfigurable processing circuit includes a first memory configured to store an input activation state, a second memory configured to store a weight, a multiplier configured to multiply the weight and the input activation state and output a product, a first multiplexer (mux) configured to, based on a first selector, output a previous sum from a previous reconfigurable processing element, a third memory configured to store a first sum, a second mux configured to, based on a second selector, output the previous sum or the first sum, an adder configured to add the product and the previous sum or the first sum to output a second sum, and a third mux configured to, based on a third selector, output the second sum or the previous sum.
Inventor(s): Hiroki Noguchi of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Der Chih of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00, G11C11/22, G11C11/16
Abstract: a memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
Inventor(s): Martin Christopher HOLLAND of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02, H01L21/762, C30B29/08, H01L29/78, C30B19/10, C30B19/12, C30B29/06, H01L29/06, H01L29/04
Abstract: a semiconductor device is provided. the semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.
Inventor(s): Shih-Yen LIN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Cheng TSAI of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Wei ZHANG of Hualien County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/28, H01L21/8234, H01L29/423, H01L21/02, H01L29/78
Abstract: a method includes forming a -d material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the -d material semiconductor layer, while leaving a portion of the -d material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the -d material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.
Inventor(s): Jia-Chuan You of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Ting Pan of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/8238, H01L23/532, H01L23/535, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
Abstract: devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (sti) feature and between the first and second gate structures. at least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.
Inventor(s): Jerry Chang-Jui KAO of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Zhong ZHUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chung HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Yen YEH of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chen CHIEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Chan YANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Ying LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/822, H01L21/48, H01L23/535, H01L23/50
Abstract: an integrated circuit includes a first cell and a second cell. the first cell has a first height along a first direction. the second cell has a second height shorter than the first height along the first direction. a transistor of the first cell and a transistor of the second cell share a first active area, and a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction.
Inventor(s): Te-Chih HSIUNG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jyun-De WU of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Peng WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Just LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L29/40, H01L21/768, H01L23/522, H01L29/423, H01L29/786
Abstract: a device includes source/drain epitaxial structures over a substrate, source/drain contacts over the source/drain epitaxial structures, respectively, a gate structure laterally between the source/drain contacts, a gate dielectric cap over the gate structure, an oxide-based etch-resistant layer over the gate dielectric cap, a nitride-based etch stop layer over the oxide-based etch-resistant layer, and an interlayer dielectric (ild) layer over the nitride-based etch stop layer. the device further includes a via structure extending through the ild layer, the nitride-based etch stop layer, and the oxide-based etch-resistant layer to electrically connect with the one of the source/drain contacts.
Inventor(s): Wei-De HO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Sheng Tang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Han-Wei Wu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Hsiang Lung of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hua-Tai Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Jung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/66, H01L21/02, H01J37/32, G03F7/00
Abstract: in a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. the overlay offset data is determined based on the received thickness variation data. the overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. a location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. the second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.
Inventor(s): Wensen Hung of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L23/42, H01L23/00
Abstract: a 3d semiconductor package provided herein includes a package substrate; a semiconductor package bonded to the package substrate; a heat dissipation unit attached to the semiconductor package, wherein the heat dissipation unit comprises a first heat dissipation component and a second heat dissipation component attached to the first heat dissipation component; and a first interface material disposed between the first heat dissipation component and the second heat dissipation component, wherein the first interface material is a phase change material.
Inventor(s): Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Yuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Chang Ku of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/433, H01L23/00, H01L21/48, H01L21/56
Abstract: disclosed are a semiconductor structure and a manufacturing method of a semiconductor structure. in one embodiment, the semiconductor structure includes a first semiconductor element, a second semiconductor element, a heat dissipation element and a gap-filling material. the second semiconductor element is on the first semiconductor element. the heat dissipation element is on the first semiconductor element and spaced apart from the second semiconductor element by a gap. the gap-filling material is filled in the gap between the second semiconductor element and the heat dissipation element.
Inventor(s): Chung-Liang CHENG of Changhua City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Shiung TSAI of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L21/02, H01L29/66, H01L29/423, H01L29/78, H01L29/06
Abstract: some implementations described herein provide a semiconductor device and methods of formation. the semiconductor device includes a transistor structure that is electrically connected to a metal layer. described techniques include forming an interconnect structure that electrically connects the metal layer to a backside power rail structure. the techniques include forming a first portion of the interconnect structure using a layer of silicon germanium as an etch stop and, after removal of the layer of the silicon germanium, forming a second portion of the interconnect structure.
Inventor(s): Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Ying LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yueh-Ching PAI of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L29/08, H01L23/522, H01L29/417
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. the device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.
Inventor(s): Kuo-Chiang TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jeng-Ya YEH of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mu-Chi CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/535, H01L29/08, H01L29/417, H01L29/78, H01L29/06, H01L29/423, H01L29/786, H01L29/775, H01L29/40, H01L21/768
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a gate structure formed over a fin structure. the semiconductor device structure includes an s/d structure formed over the fin structure and adjacent to the gate structure, and a first dielectric layer formed over the gate structure and the s/d structure. the semiconductor device structure includes an s/d contact structure formed in the first dielectric layer, and a second dielectric layer formed over the s/d contact structure. the semiconductor device structure includes a first conductive via formed in the second dielectric layer, and the first conductive via is directly over the s/d contact structure or directly over the gate structure. the first conductive via has a protruding portion that is lower than the top surface of the s/d contact structure or lower than the top surface of the gate structure.
Inventor(s): Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/498, H01L25/18, H01L25/00, H01L21/48
Abstract: semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (sois) package. the sois package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. the integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. in some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. the integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. the sois package may also include an interposer connected to the integrated fan out structure for external connection to the sois
Inventor(s): Chin-Liang Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Cheng Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Min Liang of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Wei Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/538, H01L21/48
Abstract: a semiconductor package provided herein includes a package substrate and a semiconductor device. the package substrate includes a redistribution structure, an interconnect structure bonded to the interconnect structure and an insulation material laterally surrounding the interconnect structure, wherein the redistribution structure has a reduced structure and the insulation material fills the reduced structure. the semiconductor device is bonded to the package substrate. in addition, a method of fabricating a semiconductor package is also provided and includes a precut process forming the reduced structure in the redistribution structure of the package substrate.
Inventor(s): Wei-Yu Chen of (US) for taiwan semiconductor manufacturing co., ltd., Hua-Wei Tseng of (US) for taiwan semiconductor manufacturing co., ltd., Li-Hsien Huang of (US) for taiwan semiconductor manufacturing co., ltd., Yinlung Lu of (US) for taiwan semiconductor manufacturing co., ltd., Jun He of (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L25/065, H01L23/48
Abstract: a package structure is provided. the package structure includes a bottom die and a top die. the bottom die includes: a first active region surrounded by a first seal ring region; a first seal ring region including a bottom seal ring; and a first bonding layer disposed on a front side of the bottom die. the top die includes: a second active region surrounded by a second seal ring region; a second seal ring region including a top seal ring; and a second bonding layer disposed on a front side of the top die. the bottom die and the top die are bonded through hybrid bonding between the first bonding layer and the second bonding layer at an interface therebetween such that the bottom seal ring and the top seal ring are vertically aligned and are operable to form a continuous seal ring.
Inventor(s): Zheng-Yong LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ting YEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Yun PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Keng-Chu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00
Abstract: a method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.
Inventor(s): Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jian-Wei Hong of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00
Abstract: a manufacturing method of a package is provided. the method includes the following steps. a wafer substrate having first bonding pads is provided. a die is placed on the wafer substrate, wherein the die comprises second bonding pads bonded to the first bonding pads. the die is encapsulated by an etch stop layer and a first encapsulant. a redistribution structure is disposed over the die, the etch stop layer and the first encapsulant. a portion of the redistribution structure is removed to expose the first encapsulant. the first encapsulant is removed to expose the etch stop layer. a dielectric structure is disposed over the exposed etch stop layer and laterally encapsulates the die and the redistribution structure.
Inventor(s): Chi-Yi Chuang of Kaohsiung (TW) for taiwan semiconductor manufacturing co., ltd., Hou-Yu Chen of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L23/528, H01L23/00, H01L25/00, H01L29/06, H01L29/423, H01L29/45, H01L29/786
Abstract: methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. in an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.
Inventor(s): Hsiao-Ching Huang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Fu Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Hua Hsu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Pin-Chen Chen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chang Jong of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L21/8249
Abstract: the ability of a grounded gate nmos (ggnmos) device to withstand and protect against human body model (hbm) electrostatic discharge (esd) events is greatly increased by resistance balancing straps. the resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a mosfet of the ggnmos device and a bulk ring that surrounds the active area. a vss rail is coupled to the substrate beneath the mosfet through the bulk ring. the substrate beneath the mosfet provides base regions for parasitic transistors that switch on for the ggnmos device to operate. the straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggnmos device from being switched off while a remaining portion of the ggnmos device remains switched on. the strap may be divided into segments inserted at strategic locations.
Inventor(s): Ming-Yang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung Feng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Heng Hsieh of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Bao-Ru Young of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L29/66, H01L29/78, H01L21/8234
Abstract: semiconductor structures and methods are provided. a method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. the method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.
Inventor(s): Yu-Hung CHENG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ching I LI of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/12, H01L23/66, H01L21/762
Abstract: an insulator layer of a trap-rich silicon-on-insulator (soi) wafer is formed on a trapping layer over a high-temperature substrate instead of forming the insulator layer on a bulk silicon substrate. the silicon layer of the trap-rich soi wafer is formed on a second wafer and is bonded to the insulator layer that was grown on the trapping layer. the second wafer is then removed by grinding, polishing, and/or another technique such that no cutting of the silicon device layer is performed, and therefore little to no surface damage is caused to the silicon layer. accordingly, a high-temperature annealing operation to remove surface damage that would otherwise be caused by cutting of the silicon layer may be omitted. thus, operations to form the trap-rich soi wafer may be performed at lower temperatures, which enables the trapping layer of the trap-rich soi wafer to be formed to a lesser thickness.
Inventor(s): Chung-Liang CHENG of Changhua City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chan LI of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Yi YU of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Yuan TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: doping a liner of a trench isolation structure with fluorine reduces dark current from a photodiode. for example, the fluorine may be added to a passivation layer surrounding a backside deep trench isolation structure. as a result, sensitivity of the photodiode is increased. additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.
Inventor(s): Chung-Liang CHENG of Changhua City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Yi YU of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Yuan TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: doping a liner of a trench isolation structure with zinc and/or gallium reduces dark current from a photodiode. for example, the zinc and/or gallium may be deposited on a temporary oxide layer and driven into a high-k layer surrounding a deep trench isolation structure and an interface between the high-k layer and surrounding silicon. in another example, the zinc and/or gallium may be deposited on an oxide layer between the high-k layer and surrounding silicon. as a result, sensitivity of the photodiode is increased. additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.
Inventor(s): Wen-I Hsu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Hung Chen of (US) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Chi Hung of Chu-Bel City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chang Kuo of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. the photodetectors are disposed respectively within a plurality of pixel regions. a floating diffusion node is disposed along a front-side surface of the substrate at a middle region of the plurality of pixel regions. a plurality of well regions is disposed within the substrate at corners of the plurality of pixel regions. an isolation structure extends into a back-side surface of the substrate. the isolation structure comprises a plurality of elongated isolation components disposed between adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and multiple peripheral isolation components aligned with the plurality of well regions. the elongated isolation components have a first height and the middle and peripheral isolation components have a second height less than the first height.
Inventor(s): Po Chun Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ping-Hao Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kun-Hui Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Lee of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: a semiconductor structure is disclosed. the semiconductor structure includes a number of pixels and neighboring pixels are isolated by deep trench isolation structures. in an embodiment, a method of forming the semiconductor structure includes epitaxially growing a p-type semiconductor layer on a substrate, epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer, after the epitaxially growing of the n-type semiconductor layer, forming a p-type well in the n-type semiconductor layer, forming an n-type doped region in the n-type semiconductor layer and surrounded by the p-type well, forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well, and forming a first isolation structure in the first trench.
Inventor(s): Szu-Hua Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Ming Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Yu Lin of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yen Woon of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Jie Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Gang Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Tai-Chun Huang of Hsin-Chu city (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Chang Wen of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Szuya Liao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L29/08, H01L21/28
Abstract: a semiconductor device having a low-k isolation structure and a method for forming the same are provided. the semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. a low-k dielectric material in the channel isolation structure comprises boron nitride.
Inventor(s): I-Wen Huang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Feng Fu of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Ren Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/285, H01L21/768
Abstract: a semiconductor device and a method are provided. the semiconductor device includes gate structures extending on a substrate along a first direction and arranged in a second direction in parallel with one another, source and drain regions disposed in the substrate between the parallel gate structures, and dielectric structures disposed on the substrate and between the gate structures. the semiconductor device further includes an ild layer disposed over the gate structures and the dielectric structures, contact structures disposed beside and between the parallel gate structures and separators embedded in the ild layer. each contact structure extends vertically through the ild layer and the dielectric structures, and the separators are disposed above the gate structures and disposed beside the contact structures. each contact structure extends along the first direction and extends between two adjacent separators, and each separator extending in the second direction overlaps at least two adjacent gate structures.
Inventor(s): Meng-Huan JAO of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Tianzhong Township (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L29/40
Abstract: semiconductor structures and methods for forming the same are provided. the semiconductor structure includes a gate structure formed over a substrate, and a source/drain (s/d) structure formed adjacent to the gate structure. the semiconductor structure includes a gate spacer formed adjacent to the gate structure, and an etching stop layer adjacent to the gate spacer. the semiconductor structure also includes a gate mask layer formed over the gate structure, and a topmost surface of the gate mask layer is higher than a top surface of the etching stop layer.
20240030302.MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yu-Chu LIN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Chung JEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Di WANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Yang KO of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Men-Hsi TSAI of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L29/788, H01L21/28, H01L29/66, H10B41/10, H10B41/30
Abstract: a memory device includes a semiconductor substrate, a first continuous floating gate structure, a dielectric layer, and a control gate electrode. the semiconductor substrate has a first active region. the first continuous floating gate structure is over the first active region of the semiconductor substrate, wherein the first continuous floating gate structure has first and second inner sidewalls facing each other. the dielectric layer has a first portion extending along the first inner sidewall of the first continuous floating gate structure and a second portion extending along the second inner sidewall of the first continuous floating gate structure. the control gate electrode is over the dielectric layer. the control gate electrode is in contact with the first and second portions of the dielectric layer.
Inventor(s): Lo-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Xuan HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/311, H01L29/06, H01L29/417, H01L29/423
Abstract: a method includes forming first semiconductor layers vertically stacked over a substrate; forming a gate structure over the first semiconductor layers; etching portions of the first semiconductor layers and the substrate uncovered by the substrate to form recesses; forming a spacer layer covering sidewalls of portions of the first semiconductor layers, while a bottommost one of the first semiconductor layers is uncovered by the spacer layer; etching the bottommost one of the first semiconductor layers to form a gap; forming a blocking dielectric in the gap; and forming source/drain epitaxy structures in the recesses and on opposite sides of the gate structure.
Inventor(s): I-Ming CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Sheng HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Pi CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lo-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Ju FAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huang-Lin CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/768, H01L21/8234
Abstract: a semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-align contact (sac) layer disposed on the semiconductor fin. at least a part of the sac layer is implanted with at least one implantation element. the semiconductor fin is spaced apart from the contact plug by the sac layer.
Inventor(s): Kuo-Ju CHEN of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ting CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Kang HO of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Su-Hao LIU of Chiayi County (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia YEO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66
Abstract: a method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; etching back the dummy gate layer; performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer, wherein a vertical thickness of the dummy gate layer is greater than a vertical thickness of the implantation region; forming a patterned hard mask stack over the implantation region; patterning the implantation region and the dummy gate layer by using the patterned hard mask stack as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.
Inventor(s): Lo-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Zhen YU of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/423, H01L29/06, H01L21/311, H01L29/775
Abstract: a method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.
Inventor(s): Heng-Wen TING of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia YEO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Yu TANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/78, H01L29/08
Abstract: a method for manufacturing a semiconductor device is provided. the method includes forming a semiconductor fin over a semiconductor substrate; forming a gate structure over a first portion of the semiconductor fin; etching a source/drain recess over a second portion of the semiconductor fin; and performing an in-situ source/drain etching and epitaxy process to form a source/drain epitaxial structure in the second portion of the semiconductor fin. the step of performing the in-situ source/drain etching and epitaxy process comprises performing a dry etching process to adjust a profile of the source/drain recess in a chamber; and after adjusting the dry etching process, epitaxially growing the source/drain epitaxial structure in the source/drain recess in the chamber.
Inventor(s): Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yueh-Ching PAI of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L27/088, H01L29/78, H01L21/8234
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a first plurality of vertically aligned semiconductor layers disposed over a substrate and a first gate electrode layer surrounding each of the first plurality of vertically aligned semiconductor layers. the first gate electrode layer includes first one or more work function metal layers disposed between adjacent semiconductor layers of the first plurality of vertically aligned semiconductor layers and two first conductive layers disposed on opposite sides of the first one or more work function metal layers. the first conductive layers include a material different from the first one or more work function metal layers. the first gate electrode layer further includes a second conductive layer disposed on the first conductive layers, and the second conductive layer and the first conductive layers include a same material.
Inventor(s): Bo-Feng Young of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Po-Chi Wu of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Che-Cheng Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/78, H01L21/3065, H01L29/10
Abstract: a manufacturing process and device are provided in which a first opening in formed within a substrate. the first opening is reshaped into a second opening using a second etching process. the second etching process is performed with a radical etch in which neutral ions are utilized. as such, substrate push is reduced.
Inventor(s): Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Ang Chao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lain-Jong Li of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/76, H01L29/24, H01L29/417, H01L29/66, H01L29/786, H01L21/02
Abstract: a transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. the fin structures are disposed on a material layer. the fin structures are arranged in parallel and extending in a first direction. the source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. the channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. the gate structure is disposed on the channel layers and across the fin structures. the gate structure extends in a second direction perpendicular to the first direction. the materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
20240030354.SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yu-Ru LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Han CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Shao LI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Heng CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chi On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/423, H01L29/417, H01L29/66, H01L21/3065, H01L21/02
Abstract: a device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. the first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. the gate structure surrounds the first and second channel layers. the source/drain epitaxial structure is connected to the first and second channel layers. the source/drain contact is connected to the source/drain epitaxial structure. the second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.
Inventor(s): Chia-Chen Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yangsyu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Takaaki Nakazato of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hao Hsu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jen Liao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jonathan Tsung-Yung Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K19/0185, H03K17/693, H03K19/00
Abstract: a circuit includes a control circuit configured to receive a selection signal transitioning within a first voltage domain; and generate, based on the selection signal, a first control signal transitioning within a second voltage domain different from the first voltage domain. the circuit further includes a switch circuit operatively coupled to the control circuit and comprising a first header transistor coupled to a first voltage supply transitioning within the second voltage domain, and gated by the first control signal; and a second header transistor coupled to a second voltage supply transitioning within the first voltage domain, and gated by a second control signal that is logically inverse to the first control signal. the first header transistor and the second header transistor are complementarily turned on so as to provide an output voltage equal to either the first voltage supply or the second voltage supply.
Inventor(s): Jing DING of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Zhang-Ying YAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Ting CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K19/0185, H03K3/356
Abstract: a semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (sblss) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second sblss between a normal state and a standby state when a control signal is received from the control circuit.
Inventor(s): Ying HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Changlin HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jing DING of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K19/0185, G06F30/392
Abstract: a method of generating an integrated circuit (ic) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an ic layout diagram of the cell in a storage device.
Inventor(s): Peng-Chun Liou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ya-Yun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Wei Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B12/00
Abstract: a memory device includes a semiconductor substrate. the memory device includes a stack of channel layers over the semiconductor substrate, each channel layer including an oxide material. the memory device includes a word line structure interleaved with the stack of channel layers. the memory device includes a source feature and a drain feature on both sides of the stack of channel layers.
Inventor(s): Song-Fu Liao of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chang Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/11597, H01L27/11587, H01L29/51, H01L29/66, H01L29/78
Abstract: in some embodiments, the present disclosure relates to a 3d memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chen Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/30, H01L29/786, H01L29/06, H01L29/423, H01L29/24, H10B51/20, H10B51/40
Abstract: a memory device, a semiconductor device and a manufacturing method of the memory device are provided. the memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. the first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. the third stacking structure is located between the first and second stacking structures. the first channel structure extends between the channel layers in the first and third stacking structures. the second channel structure extends between the channel layers in the second and third stacking structures. the gate dielectric layer and the first gate structure wrap around the first channel structure. the switching layer and the second gate structure wrap around the second channel structure.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Piao Chiu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Chiang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Sheng Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B63/00, H10N70/00, H10N70/20
Abstract: a memory device includes a first electrode, a selector layer and a plurality of first work function layers. the first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on January 25th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B24B53/017
- B24B53/12
- Taiwan semiconductor manufacturing co., ltd.
- G01N31/22
- G01N33/18
- G01R31/265
- G06F3/06
- G11C11/419
- G11C7/10
- G11C8/16
- G06N3/063
- G06F11/10
- G11C11/16
- G11C29/52
- G06F30/392
- G06F11/32
- G06F30/398
- G06N3/04
- G11C13/00
- G11C11/22
- H01L21/02
- H01L21/762
- C30B29/08
- H01L29/78
- C30B19/10
- C30B19/12
- C30B29/06
- H01L29/06
- H01L29/04
- H01L21/28
- H01L21/8234
- H01L29/423
- H01L21/768
- H01L21/8238
- H01L23/532
- H01L23/535
- H01L27/092
- H01L29/66
- H01L29/786
- H01L21/822
- H01L21/48
- H01L23/50
- H01L29/40
- H01L23/522
- H01L21/66
- H01J37/32
- G03F7/00
- H01L23/367
- H01L23/42
- H01L23/00
- H01L23/433
- H01L21/56
- H01L23/528
- H01L29/08
- H01L29/417
- H01L29/775
- H01L23/538
- H01L23/498
- H01L25/18
- H01L25/00
- H01L25/065
- H01L23/48
- H01L29/45
- H01L27/02
- H01L21/8249
- H01L27/088
- H01L27/12
- H01L23/66
- H01L27/146
- H01L21/285
- H01L29/788
- H10B41/10
- H10B41/30
- H01L21/311
- H01L21/3065
- H01L29/10
- H01L29/76
- H01L29/24
- H03K19/0185
- H03K17/693
- H03K19/00
- H03K3/356
- H10B12/00
- H01L27/11597
- H01L27/11587
- H01L29/51
- H10B51/30
- H10B51/20
- H10B51/40
- H10B63/00
- H10N70/00
- H10N70/20
- H01L29/42392
