Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on February 1st, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on February 1st, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 67 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L23/00 (16), H01L23/498 (11), H01L23/31 (10), H01L21/78 (10), H01L23/522 (9)
With keywords such as: structure, layer, disposed, semiconductor, substrate, gate, forming, source, dielectric, and device in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Pei-Wei Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Fu Wei Liu of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Hsien Lee of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Chung Wu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Yu Ku of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming -Ji Lii of Sinpu Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B81B7/00, B81C1/00
Abstract: a method includes forming an interconnect structure over a semiconductor substrate. the interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. a plurality of metal pads are formed over the interconnect structure. a plurality of through-holes are formed to penetrate through the wafer. the plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. the middle portions are wider than respective ones of the top portions. a metal layer is formed to electrically connect to the plurality of metal pads. the metal layer extends into the top portions of the plurality of through-holes.
Inventor(s): Wei Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Wen Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Wei Su of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N27/403, G01N27/414
Abstract: a substrate has a first side and a second side vertically opposite to the first side. a sensing transistor is disposed at least in part over the first side of the substrate. a plurality of voltage reference transistors is disposed at least in part over the first side of the substrate. the voltage reference transistors are disposed on different lateral sides of the sensing transistor. a structure is disposed over the second side of the substrate. the structure defines one or more openings configured to collect a fluid. a sensing film is disposed over the second side of the substrate, wherein the sensing transistor is configured to detect, at least in part through capacitive coupling, a presence of one or more predefined miniature targets in the fluid that attach to the sensing film in the opening that is vertically aligned with the sensing transistor.
Inventor(s): Wei Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Katherine H. Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Wen Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Wei Su of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N27/414, G01N27/327
Abstract: a substrate has a first side and a second side opposite the first side. a first transistor has a first gate, a second transistor has a second gate, and a third transistor has a third gate. the first gate, the second gate, and the third gate are each disposed over the first side of the substrate. the second gate is disposed between the first gate and the third gate. the first gate and the third gate have different material compositions. a structure is disposed over the second side of the substrate. the structure includes a first opening aligned with the first transistor, a second opening aligned with the second transistor, and a third opening aligned with the third transistor. a sensing film is disposed over the second side of the substrate. the sensing film is configured to attach to one or more predefined miniature targets.
Inventor(s): Yi-Hsing Hsiao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jie Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Tsun Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N33/543, G01N33/569, G01N27/414, B01L3/00
Abstract: a fluidic cartridge module includes a casing, a biosensor package, and a fluidic channel. the casing includes a sample inlet and a buffer inlet, a biosensor package disposed in the casing and comprising a sensor array and a reference electrode. the fluidic channel is disposed over the biosensor package and connected to the sample inlet and the buffer inlet, wherein the fluidic channel includes a first opening aligned with the sensor array and a second opening aligned with the reference electrode.
Inventor(s): Chien-Yi Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kao-Chih Liu of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chia Hong Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ting Lin of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Min-Feng Ku of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01R31/28, H01L23/522, G01R1/04
Abstract: a socket of a testing tool is configured to provide testing signals. a device-under-test (dut) board is configured to provide electrical routing. an integrated circuit (ic) die is disposed between the socket and the dut board. the testing signals are electrically routed to the ic die through the dut board. the ic die includes a substrate in which plurality of transistors is formed. a first structure contains a plurality of first metallization components. a second structure contains a plurality of second metallization components. the first structure is disposed over a first side of the substrate. the second structure is disposed over a second side of the substrate opposite the first side. a trench extends through the dut board and extends partially into the ic die from the second side. a signal detection tool is configured to detect electrical or optical signals generated by the ic die.
Inventor(s): Wei-Hao LEE of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Cheng HSU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Tung KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Chang LEE of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/62
Abstract: in a method of manufacturing a pellicle for an extreme ultraviolet (euv) photomask, a membrane of spcarbon is formed, a treatment is performed on the membrane to change a surface property of the membrane, and after the treatment, a cover layer is formed over the membrane.
Inventor(s): Pei-Cheng HSU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Pi Sun of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Chang Lee of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/64, G03F1/22, C01B32/168
Abstract: in a method of manufacturing a pellicle for an extreme ultraviolet (euv) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a joule hearting treatment is performed to the nanotube layer by applying electric current through the nanotube layer.
Inventor(s): Zheng-Jun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Cheng Chou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Der Chih of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chin-I Su of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G05F1/575, G05F1/565
Abstract: a voltage regulator circuit is provided. the voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. a plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. a feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. the feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. the voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
Inventor(s): Chih-yuan Stephen YU of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Boh-Yi HUANG of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Chao-Chun LO of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Xiang GUO of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/323, G06F30/392, G06F30/327
Abstract: a method and system for migrating an existing asic design from one semiconductor fabrication process to another are disclosed herein. in some embodiments, a method for migrating the existing asic design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the asic design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the asic design in terms of the equivalent target standard cells.
20240037309.MULTIPLEXER_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chi-Lin Liu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Chih Hsieh of Yangmei City (TW) for taiwan semiconductor manufacturing co., ltd., Jian-Sing Li of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Hsiang Ma of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsun Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheok-Kei Lei of Macau MO (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/392, G06F30/347, G06F30/39, H01L27/02
Abstract: a multiplexer circuit includes first and second fins each extending in an x-axis direction. first, second, third and fourth gates extend in a y-axis direction perpendicular to the x-axis direction and contact the first and second fins. the first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. fifth, sixth, seventh and eighth gates extend in the y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. an input logic circuit is configured to provide an output at an intermediate node. a ninth gate extends in the y-axis direction and contacts the first and second fins. an output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
Inventor(s): Tzu-Yu Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Wen Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11B9/02, H10B51/30
Abstract: the present disclosure relates to an integrated chip. the integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. a ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. one or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. the ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
Inventor(s): Ku-Feng Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jui-Che Tsai of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Perng-Fei Yuh of Walnut Creek CA (US) for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C7/06, H01L27/06, H03K3/037, H03K3/356
Abstract: a sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. the latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. the first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.
Inventor(s): Yorinobu FUJINO of Kanagawa (JP) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/419
Abstract: a memory device is provided, including a first word line coupled to a first memory cell, a second word line coupled to a second memory cell, and a read assist circuit coupled between the first and second word lines, and in a first time period configured, in response to a first control signal, to adjust a voltage level of the first word line to a first voltage and to adjust a voltage level of the second word line to a second voltage. in some embodiments, the first voltage is smaller than a first supply voltage, and the second voltage is greater than a second supply voltage smaller than the first supply voltage.
Inventor(s): Yu-Ching Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Kuang Kao of Chu-pei City (TW) for taiwan semiconductor manufacturing co., ltd., Huei-Wen Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/248, H01J37/305, H01J37/30, H01J37/28
Abstract: an apparatus for observing a sample using a charged particle beam includes an ion beam column configured to generate and direct an ion beam, an electron beam column configured to generate and direct an electron beam, a vacuum chamber for housing the sample, and a probe positioned in the vacuum chamber. the probe is configured to provide electrical connection between the sample and a power supply.
Inventor(s): Kai-Fang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02, C23C16/455, C23C16/30, H01L21/768, H01L23/522
Abstract: a method for manufacturing a semiconductor structure includes: forming a dielectric layer on a base structure; forming a trench in the dielectric layer to expose the base structure; forming a metal contact in the trench; and performing a plurality of first atomic layer deposition (ald) cycles to form a plurality of first atomic layers which cover the dielectric layer and the metal contact and which serve as an etch stop layer. each of the first ald cycles includes: forming a corresponding one of the first atomic layers; and performing a treatment to convert the corresponding first atomic layer into monocrystalline phase at a temperature not greater than 425� c.
20240038571.VACUUM CHUCK_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Po-Yo SU of Keelung City (TW) for taiwan semiconductor manufacturing co., ltd., Young-Wei LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yu Liang HUANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ching LEE of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Chun PENG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chen Liang CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo Hui CHANG of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/683, H01L21/687
Abstract: at least one embodiment, a vacuum chuck includes a moisture gate structure that allows for moisture to escape to reduce an amount of warpage in a workpiece when present on the vacuum chuck. the moisture gate structure includes a base portion that extends laterally outward from a central vacuum portion of the vacuum chuck, and a plurality of protrusions are spaced apart from the central vacuum portion and extend outward from the base portion. end surfaces of the plurality of protrusions contact a backside surface of the workpiece (e.g., a wafer on a carrier) when the workpiece is present on the vacuum chuck. the vacuum chuck may further include one or more guide portions that act as guides such that the workpiece remains properly aligned and within position when present on the vacuum chuck.
Inventor(s): Kai-Fang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/535, H01L23/532
Abstract: a semiconductor structure includes a base structure, a plurality of electrically conductive features disposed on the base structure, and an isolation structure disposed on the base structure. the base structure includes a substrate. the electrically conductive features are spaced apart from each other. the isolation structure includes a first inter-metal dielectric feature extending horizontally to interconnect the electrically conductive features, a first air gap layer disposed in the isolation structure and around the electrically conductive features, and a first sustaining feature extending horizontally to interconnect the electrically conductive features and disposed between the first inter-metal dielectric feature and the first air gap layer. methods for manufacturing the semiconductor structure are also disclosed.
Inventor(s): Kao-Chih Liu of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Wenmin Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsuan Jung Chiu of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ting Lin of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia Hong Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, G01R31/28
Abstract: a semiconductor substrate includes a plurality of transistors. a first structure is disposed over a first side of the semiconductor substrate. the first structure contains a plurality of first metallization components. a carrier substrate is disposed over the first structure. the first structure is located between the carrier substrate and the semiconductor substrate. one or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. a second structure is disposed over a second side of the semiconductor substrate opposite the first side. the second structure contains a plurality of second metallization components.
Inventor(s): Chung-Hao Cai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hsien Yao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Jun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L27/088
Abstract: a method includes forming first and second fins disposed on a substrate, forming a gate structure over the first and second fins, epitaxially growing a first source/drain (s/d) feature on the first fin and a second s/d feature on the second fin, depositing a dielectric layer covering the first and second s/d features, etching the dielectric layer to form a trench exposing the first and second s/d features, forming a metal structure in the trench and extending from the first s/d feature to the second s/d feature, performing a cut metal process to form an opening dividing the metal structure into a first segment over the first s/d feature and a second segment over the second s/d feature, and depositing an isolation feature in the opening. the isolation feature separates the first segment from the second segment.
Inventor(s): Kuan-Kan HU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jhih-Rong HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Bo LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Min-Chiang CHUANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Li WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yen WOON of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Szuya LIAO of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/08, H01L29/417, H01L29/45, H01L21/285
Abstract: a method for manufacturing a semiconductor device is provided. the method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.
Inventor(s): Yu-Ching Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Kuang Kao of Chu-pei City (TW) for taiwan semiconductor manufacturing co., ltd., Huei-Wen Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/66
Abstract: a testline structure of a semiconductor device includes a substrate layer, a frontside insulating layer atop the substrate layer, a backside insulating layer under the substrate layer, and a probe pad structure vertically extending through the frontside insulating layer, the substrate layer, and the backside insulating layer. the probe pad structure includes a frontside probe pad in the frontside insulating layer and a backside probe pad in the backside insulating layer.
Inventor(s): Cheng-Chieh Li of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L25/065, H01L23/00, H01L21/56, H01L23/31, H01L23/373
Abstract: disclosed are a semiconductor package and a manufacturing method of a semiconductor package. in one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, a first encapsulant, at least one heat dissipation element and a second encapsulant. the plurality of semiconductor dies are disposed on the interposer substrate. the first encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies. the at least one heat dissipation element is disposed on the plurality of semiconductor dies. the second encapsulant is disposed on the first encapsulant and surrounds the at least one heat dissipation element.
Inventor(s): Wensen Hung of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Syuan Li of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L23/053, H01L23/42, H01L21/52, H01L23/00
Abstract: a package structure includes a substrate, a semiconductor package disposed over the substrate, a first lid structure disposed over the substrate, and a second lid structure disposed over the semiconductor package and the first lid structure. the first lid structure includes an opening exposing a region of the semiconductor package. a thermal interface material is disposed between the second lid structure and the semiconductor package, and a phase change adhesive is disposed between the second lid structure and the first lid structure.
Inventor(s): Ping-Yin Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Huan Liao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pu Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Hui Cheng of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/373, H01L23/367, H01L23/31, H01L23/498, H01L21/48, H01L21/56
Abstract: in an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. the device also includes a back-side metal layer on a back-side of the package component. the device also includes an indium thermal interface material on a back-side of the back-side metal layer. the device also includes a lid on a back-side of the indium thermal interface material. the device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.
Inventor(s): Kai-Fung Chang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Feng Weng of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Yu Yen of MiaoLi County (TW) for taiwan semiconductor manufacturing co., ltd., Kai-Ming Chiang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Jhan Tsai of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Wei Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/373, H01L23/498, H01L23/00, H01L23/31, H01L21/48, H01L21/56, H01L21/78
Abstract: a semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. the semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. the electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally couped to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.
Inventor(s): Wensen Hung of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/42, H01L21/48, H01L25/16, H01L23/31, H01L23/498, H01L21/56, H01L23/00
Abstract: a method includes attaching a permeable plate to a metal lid, with the permeable plate including a metallic material, and dispensing a liquid-metal-comprising media to a first package component. the first package component is over and bonded to a second package component. the liquid-metal-comprising media includes a liquid metal therein. the method further includes attaching the metal lid to the second package component. during the attaching, the liquid-metal-comprising media migrates into the permeable plate to form a composite thermal interface material.
Inventor(s): Chi-Yang Yu of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Liang Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Cheng Hou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jung Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Min Liang of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L25/065, H01L21/48, H01L23/14
Abstract: semiconductor device packages and methods of forming the same are discussed. in an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.
Inventor(s): Ting-Ting KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Hsien HUANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Tien-Chung YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Chun CHUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yinlung LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jun HE of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L25/16, H01L23/00, H01L21/48, H01L23/14
Abstract: an adhesion layer may be formed over portions of a redistribution layer (rdl) in a redistribution structure of a semiconductor device package. the portions of the rdl over which the adhesion layer is formed may be located in the “shadow” of (e.g., the areas under and/or over and within the perimeter of) one or more tivs that are connected with the redistribution layer structure. the adhesion layer, along with a seed layer on which the portions of the rdl are formed, encapsulate the portions of the rdl in the shadow of the one or more tivs, which promotes and/or increases adhesion between the portions of the rdl and the polymer layers of the redistribution structure.
Inventor(s): Kuo-Chiang Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Hsuan Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jeng-Ya Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Mu-Chi Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L29/40, H01L29/417, H01L29/08, H01L23/522, H01L21/8234, H01L27/088
Abstract: a semiconductor device includes a source region and a drain region, a first source contact, a first drain contact, a first drain via and a first source via. the source region and the drain region are located over a substrate. the first source contact is disposed on the source region, and the first drain contact is disposed on the drain region. the first drain via is connected to the first drain contact, wherein the first drain via includes a barrier-less body portion. the first source via is connected to the first source contact, wherein the first source via includes a body portion and a barrier layer surrounding the body portion, and a size of the first source via is greater than a size of the first drain via.
Inventor(s): Kai-Fang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cherng-Shiaw TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chin LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ju WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/532, H01L21/768
Abstract: an interconnection structure is provided to include an interlayer dielectric (ild) layer that is disposed over a substrate, a metal via that is disposed in the ild layer, and a metal wire that is disposed over the metal via in the ild layer and that is electrically connected to the metal via. the ild layer includes silicon carbon nitride.
Inventor(s): Kai-Fang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chin LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ju WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Yen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/532, H01L23/522, H01L21/768
Abstract: a semiconductor device includes a substrate and an interconnect layer disposed over the substrate. the interconnect layer includes a dielectric layer, an interconnect structure disposed in the dielectric layer, and an etch stop layer which is disposed on a lower end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of sicn, wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Hao Tsai of Huatan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/48, H01L23/498, H01L23/00, H01L25/10
Abstract: a method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. a second plurality of memory dies are bonded over the plurality of logic dies. the plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
Inventor(s): Yung-Chi Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jhih-Yu Wang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/00, H01L23/58
Abstract: a package includes a die and a redistribution structure. the die has an active surface and is wrapped around by an encapsulant. the redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.
Inventor(s): Tien-Chung YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Hsien HUANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Feng WU of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Sheng LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Jen CHEN of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Jun HE of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L25/10, H01L21/78, H01L21/56, H01L21/66, H01L23/498, H01L23/31
Abstract: a laser grooving operation is performed to form a plurality of grooves in a semiconductor die prior to attaching the semiconductor die to a semiconductor device package substrate. in addition to forming a first groove through which blade sawing is to be performed to separate the semiconductor die from other semiconductor dies, a second groove may be formed between the first groove and a seal ring of the semiconductor die. the second groove is configured to contain any potential delamination that might otherwise propagate to an active region of the semiconductor die. accordingly, the second groove and the associated laser grooving operation described herein may reduce the likelihood of delamination that might otherwise be caused by swelling and/or expansion in a molding compound formed around the semiconductor die after the semiconductor die is attached to the semiconductor device package substrate.
Inventor(s): Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L25/065, H01L23/58, H01L21/78
Abstract: a semiconductor device includes a first and second semiconductor chip having a respective first surface and a second surface opposite to each other. the semiconductor device can include a second semiconductor chip having a third surface and a fourth surface opposite to each other. the third surface of the second semiconductor chip can face the second surface of the first semiconductor chip. a first portion of a dielectric filling material can be in contact with a first sidewall of the first semiconductor chip. a second portion of a dielectric filling material can be in contact with a second sidewall of the second semiconductor chip. the first and second portions of the dielectric filling material can have a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip.
20240038688.SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Zi-Jheng LIU of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Jo-Lin LAN of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang HU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/538, H01L23/58, H01L23/544, H01L21/48, H01L21/78, H01L23/31, H01L21/683
Abstract: a device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. the plurality of through vias are embedded in the molding compound. the seal ring structure is over the molding compound and surrounds the through vias in a top view. the protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.
Inventor(s): Ting-Ting Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Hsien Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tien-Chung Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Chun Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yinlung Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jun He of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/538, H01L23/498, H01L23/31, H01L23/528, H01L23/522
Abstract: a semiconductor package structure is provided. the semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (rdl) structure disposed on the backside of the die; a second rdl structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (tiv) disposed lateral to the die and extending to electrically connect the first and the second rdl structures; a molding compound disposed between the first and second rdl structures; an enhancement layer disposed on the second rdl structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second rdl structure. the enhancement layer includes a plurality of cascaded openings electrically connected to the first rdl structure. each of the pre-solder bumps is disposed in one of the cascaded openings.
Inventor(s): Jeng-Nan Hung of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hang Tung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/48, H01L21/768, H01L25/065
Abstract: a method includes directly bonding a first wafer to a second wafer, wherein the bonding electrically connects a first interconnect structure of the first wafer to a second interconnect structure of the second wafer; directly bonding first semiconductor devices to the second wafer, wherein the bonding electrically connects the first semiconductor devices to the second interconnect structure; encapsulating the first semiconductor devices with a first encapsulant; and forming solder bumps over the first semiconductor devices.
Inventor(s): Wen-Ting LAN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., I-Han HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Cheng CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L25/065, H01L21/02, H01L21/265, H01L23/498, H01L23/538
Abstract: a method of forming a semiconductor structure is provided. two wafers are first bonded by oxide bonding. next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. first devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. the second devices are then formed in the active regions of the second wafer. furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.
Inventor(s): Jen-Yuan CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chih WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/10, H01L23/00, H01L23/31, H01L23/498, H01L21/48, H01L21/56, H01L25/00
Abstract: a package structure includes a package substrate, a first die, a second die, a first underfill, and a second underfill. the first die and a second die are disposed on the package substrate. the first underfill is between the first die and the package substrate, and the first underfill includes a first extension portion extending from a first sidewall of the first die toward the second die. the second underfill is between the second die and the package substrate, and the second underfill includes a second extension portion extending from a second sidewall of the second die toward the first die, the second extension portion overlapping the first extension portion on the package substrate.
20240038752.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Wei-Hung Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Min Huang of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Jung Hsueh of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Wan-Yu Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Mirng-Ji Lii of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/18, H01L21/78, H01L23/31, H01L23/498, H01L23/00
Abstract: provided are a package structure and a method of forming the same. the method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
Inventor(s): Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Johnny Chiahoa LI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Ying LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Hong GAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Chan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/118, H01L27/02, H01L21/8238, H03K3/037
Abstract: a flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. the first active region corresponds to a first set of transistors of a first type. the second active region corresponds to a second set of transistors of a second type different from the first type. the third active region corresponds to a third set of transistors of the second type. the fourth active region corresponds to a fourth set of transistors of the first type. the flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. the first gate structure is configured to receive a first clock signal.
20240038804.IMAGE SENSOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yun-Wei CHENG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hao CHOU of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hsun-Ying HUANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: an image sensor device is provided. the image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. the image sensor device includes a first isolation structure extending from the front surface into the substrate. the first isolation structure surrounds a first portion of the light-sensing region, the first isolation structure has an etch stop layer, the etch stop layer has an end portion, and the end portion has an h-like shape. the image sensor device includes a second isolation structure extending into the substrate from the back surface to the end portion. the second isolation structure surrounds a second portion of the light-sensing region.
Inventor(s): Y.W. HUANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hsien LIN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., U-Ting CHEN of Wanluan Township (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Ting TSAI of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Hsuan HSU of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: some implementations described herein provide for techniques to form a biased backside deep trench isolation and grid structure for a backside illumination image sensor. the techniques include forming an array of backside deep trench isolation structures and a biasing-pad that electrically connects to the array of metal-filled backside deep trench isolation structures through the grid structure. the array of backside deep trench isolation structures, the grid structure, and the biasing-pad structure may reduce a likelihood of electrical cross-talk and/or oblique light cross-talk between the photodiodes of the backside illumination image sensor. in this way, a performance of the backside illumination image sensor may be improved. such improvements may include a suppression of a dark current within the backside illumination image sensor, a reduction in a number of white pixels, and a reduction in cross-talk within the backside illumination image sensor.
Inventor(s): Sheng-Tsung WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Min-Hsuan LU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hung CHU of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L21/285, H01L21/311
Abstract: a method for forming a semiconductor device structure includes forming nanostructures over a front side of a substrate. the method also includes forming a gate structure surrounding the nanostructures. the method also includes forming a source/drain structure beside the gate structure. the method also includes forming a trench though the substrate from a back side of the substrate. the method also includes forming a first silicide layer in contact with the source/drain structure. the method also includes forming a second silicide layer over the first silicide layer and the sidewalls of the trench. the method also includes depositing a first conductive material over the second silicide layer. the method also includes etching back the first conductive material. the method also includes etching back the second silicide layer. the method also includes depositing a second conductive material in the trench.
Inventor(s): Wu-Wei Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yan-Yi Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Hsiang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/40, H01L29/66, H01L27/12, H01L29/786
Abstract: a semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. the at least one charged layer includes an oxide material.
Inventor(s): Chung-Hao CAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Hsun WANG of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hsien YAO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wang-Jung HSUEH of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Jun HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Kai YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L29/40, H01L21/3213, H01L21/311
Abstract: a method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.
Inventor(s): Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L27/092, H01L29/08, H01L29/45, H01L21/285, H01L21/8238
Abstract: a semiconductor device structure, along with methods of forming such, are described. the semiconductor device structure includes a first source/drain epitaxial feature disposed in a first region, and the first source/drain epitaxial feature is asymmetric with respect to a fin. the structure further includes a second source/drain epitaxial feature disposed in the first region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, and a conductive feature disposed over the first and second source/drain epitaxial features and the first dielectric feature.
Inventor(s): Chih-Ching WANG of Kinmen County (TW) for taiwan semiconductor manufacturing co., ltd., Chung-I YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsing HSIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/786, H01L29/417, H01L29/66
Abstract: a method for forming a semiconductor device structure is provided. the method includes providing a substrate. the method includes forming a nanostructure stack over the substrate. the method includes forming a gate stack over the nanostructure stack and the substrate. the method includes removing the first nanostructure forming a first gap between the substrate and the second nanostructure. the method includes forming a first spacer layer in the first gap and a gate spacer over a sidewall of the gate stack. the method includes partially removing the nanostructure stack, which is not covered by the gate stack and the gate spacer, to form a first trench in the nanostructure stack. the method includes forming a source/drain structure in the first trench and over the first spacer layer.
Inventor(s): Cheng-I Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Ming Tang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Han Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/786, H01L29/423
Abstract: gate profile tuning techniques are disclosed herein. an exemplary gate profile tuning method includes forming a gate structure over a channel layer. the gate structure includes a dummy gate and gate spacers disposed along sidewalls of the dummy gate. the method further includes partially removing the dummy gate to form a gate opening that defines a gate profile. the gate profile is then modified by treating portions of the gate spacers (for example, by oxygen plasma treatment) and removing the treated portions of the gate spacers (for example, by oxide removal). after removing a remainder of the dummy gate to expose the channel layer, a gate stack of the gate structure is formed in the gate opening. the gate stack has a funnel-shaped profile. in some embodiments, a width of the gate stack above the channel layer is greater than a width of the gate stack below the channel layer.
Inventor(s): Ya-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Yi Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Yuan Ku of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L27/092, H01L29/66, H01L21/8238
Abstract: a semiconductor device includes a transistor disposed in an active region. the transistor comprises a source/drain feature, a fin channel and a gate structure wrapping over the fin channel. the transistor also includes an insulation region disposed at an active edge. the active edge is at a boundary of the active region. the insulation region includes a trench. the trench has a tapered portion. a width of the tapered portion of the trench at a top of the fin channel is greater than a width of the tapered portion of the trench at a bottom of the gate structure.
Inventor(s): Marcus Johannes Henricus VAN DAL of Linden (BE) for taiwan semiconductor manufacturing co., ltd., Gerben DOORNBOS of Kessel-Lo (BE) for taiwan semiconductor manufacturing co., ltd., Georgios VELLIANITIS of Heverlee (BE) for taiwan semiconductor manufacturing co., ltd., Mauricio MANFRINI of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L29/66, H01L21/02, H01L21/425, H01L29/24, H10B61/00, H10B63/00
Abstract: semiconductor structures and methods for manufacturing the same are provided. the method for manufacturing the semiconductor structure includes forming a bottom electrode layer over a substrate and forming a gate dielectric layer over the bottom electrode layer. the method for manufacturing the semiconductor structure also includes forming an active layer over the gate dielectric layer and forming an indium-containing feature vertically overlapping the bottom electrode layer. the method for manufacturing the semiconductor structure also includes forming a source/drain contact landing on the indium-containing feature.
Inventor(s): Wei Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Wen Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Wei Su of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L27/12, H01L29/66, G01N33/543
Abstract: an interconnect structure is disposed over a semiconductor substrate. the interconnect structure includes a plurality of interconnect layers. a first thin-film transistor (tft) and a second tft disposed over the semiconductor substrate. the first tft and the second tft each vertically extend through at least a subset of the interconnect layers. an opening is formed in the interconnect structure. the opening is disposed between the first tft and the second tft. a sensing film is disposed over a bottom surface and side surfaces of the opening.
Inventor(s): Kuan-Ting PAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L29/78, H01L29/66, H01L29/06, H01L29/51
Abstract: a device includes: a first stack of nanostructures; a second stack of nanostructures horizontally offset from the first stack; a first source/drain region abutting the first stack of nanostructures; a second source/drain region abutting the second stack of nanostructures; a wall structure between the first and second stacks and spaced apart from the nanostructures of the first stack; and a first gate structure, which includes: a gate dielectric layer that wraps around the nanostructures of the first stack; and a conductive core layer on the gate dielectric layer, wherein thickness of the conductive core layer between one of the nanostructure of the first stack and the wall structure is in a range of 0 nanometers to 1 nanometer, inclusive.
Inventor(s): Ya-Chin KING of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chrong Jung LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shi-Jiun WANG of Changhua City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L31/119, H01L31/0224
Abstract: a device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ild) layer, a reading contact, and a sensing contact. the isolation structure laterally surrounds the active region. the gate structure is across the active region. the ild layer laterally surrounds the gate structure. the reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ild layer. the sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ild layer.
Inventor(s): Hung-Chih Ou of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hao Chen of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/012, H03K17/56
Abstract: a device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. the first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. the first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. the second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.
20240039520.CLOCK SYNTHESIZER_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Wei Shuo LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei Chih CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/017, H03K5/02, H03K5/156, H03L7/107
Abstract: a clock synthesizer is provided. a clock buffer is configured to store an input clock signal. a duty cycle corrector (dcc) circuit is connected to the clock buffer. the dcc circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. an output clock signal comprising the duty cycle corrected input clock signal is generated. the output clock signal is provided. a current source is configured to sink a clamping current to the dcc circuit.
Inventor(s): Kao-Chih Liu of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Wenmin Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ting Lin of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia Hong Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., ChienYi Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H05K1/18, H01L23/522, G01R31/28
Abstract: an integrated circuit (ic) chip assembly includes an integrated circuit (ic) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. the first structure is disposed over a first side of the first substrate. the second structure is disposed over a second side of the first substrate opposite the first side. the chip assembly includes a second substrate bonded to the ic die through the second side. the chip assembly includes a trench that extends through the second substrate and through the second structure of the ic die. sidewalls of the trench are defined at least in part by one or more protective layers.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/11, G11C11/419, G11C11/412, H01L27/105
Abstract: a method includes forming a first channel pattern on a substrate from a top view; forming first and second gate patterns extending across the first channel pattern; forming first, second, and third source/drain patterns on the first channel pattern, the first and second source/drain patterns on opposite sides of the first gate pattern and the second and third source/drain patterns on opposite sides of the second gate pattern, wherein a first channel region of the first channel pattern, the first gate pattern, and the first and second source/drain patterns form a first read pull-down transistor of a first static random access memory (sram) cell, and a second channel region of the first channel pattern, the second gate pattern, and the second and third source/drain patterns form a second read pull-down transistor of a second sram cell.
20240040763.MEMORY STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/11
Abstract: a memory structure includes a static random-access memory (sram) cell having a cell boundary. the sram cell includes a first write-port pull-up (pu) transistor and a second write-port pu transistor, a first write-port pull-down (pd) transistor, a second write-port pd transistor, a first write-port pass-gate (pg) transistor, a second write-port pg transistor, a first read-port pd transistor, a second read-port pd transistor, a first read-port pg transistor, and a second read-port pg transistor respectively including nanostructures that are vertically stacked from each other. the memory structure further includes a write bit-line conductor and a write bit-line-bar conductor in a first metal layer under the sram cell, wherein the write bit-line conductor is electrically connected to a source/drain feature of the first write-port pass-gate transistor and the write bit-line-bar conductor is electrically connected to a source/drain feature of the second write-port pass-gate transistor.
Inventor(s): Kuen-Yi Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Hai Li of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yi Ching Ong of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Ching Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsuan Chen of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Sheng Chen of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/11507
Abstract: a memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an fjt structure; and a heating structure formed around the memory cell on a plurality of sides. the fjt structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. the switching barrier includes ferroelectric (fe) material that may be polarized to store information.
Inventor(s): Tzu-Yu Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Chu-Jie Huang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Wan-Chen Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Chen Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Hung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chi Tu of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B53/30, H10B53/10, H01L23/522, H01L23/528
Abstract: various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. more particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. in some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.
Inventor(s): Ji-Feng Ying of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jhong-Sheng Wang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Tsann Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B61/00, H01L23/528, H01F10/32, H01L23/522, H01F41/32, G11C11/16, H10N50/01, H10N50/80
Abstract: a memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. the word lines are intersected with the bit lines. the auxiliary lines are disposed between the word lines and the of bit lines. the selectors are inserted between the bit lines and the auxiliary lines. the memory cells are inserted between the word lines and the auxiliary lines.
Inventor(s): Cheng-Hsien Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Feng Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Min Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing co., ltd., Elia Ambrosi of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hengyuan Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B63/00
Abstract: a memory device includes a substrate, a bottom electrode disposed over the substrate, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer. the selector layer is an oxygen-doped chalcogenide based film, and an oxygen content of the selector layer is about 10 at % or less.
Inventor(s): Ku-Feng Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/80, G11C11/16, H10B61/00, H10N50/01
Abstract: a memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. the memory device further includes a word-line driver and a bit-line driver. a first number of the source lines are connected in parallel.
Inventor(s): Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Piao Chiu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Shao-Ming Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Tien Tu of Chiayi County (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L45/00, H01L27/24
Abstract: a memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. the first signal line is disposed over the substrate. the first dielectric layer is disposed over the first signal line. the phase change layer is disposed over the first dielectric layer. the second dielectric layer is disposed over the phase change layer. the first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. the second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.
Inventor(s): Chun-Hsu Yen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chuan Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hui Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
Abstract: a method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on February 1st, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B81B7/00
- B81C1/00
- Taiwan semiconductor manufacturing co., ltd.
- G01N27/403
- G01N27/414
- G01N27/327
- G01N33/543
- G01N33/569
- B01L3/00
- G01R31/28
- H01L23/522
- G01R1/04
- G03F1/62
- G03F1/64
- G03F1/22
- C01B32/168
- G05F1/575
- G05F1/565
- G06F30/323
- G06F30/392
- G06F30/327
- G06F30/347
- G06F30/39
- H01L27/02
- G11B9/02
- H10B51/30
- G11C7/06
- H01L27/06
- H03K3/037
- H03K3/356
- G11C11/419
- H01J37/248
- H01J37/305
- H01J37/30
- H01J37/28
- H01L21/02
- C23C16/455
- C23C16/30
- H01L21/768
- H01L21/683
- H01L21/687
- H01L23/535
- H01L23/532
- H01L21/8234
- H01L27/088
- H01L21/8238
- H01L27/092
- H01L29/08
- H01L29/417
- H01L29/45
- H01L21/285
- H01L21/66
- H01L23/367
- H01L25/065
- H01L23/00
- H01L21/56
- H01L23/31
- H01L23/373
- H01L23/053
- H01L23/42
- H01L21/52
- H01L23/498
- H01L21/48
- H01L21/78
- H01L25/16
- H01L23/14
- H01L23/528
- H01L29/40
- H01L23/538
- H01L23/48
- H01L25/10
- H01L23/58
- H01L23/544
- H01L21/265
- H01L25/00
- H01L25/18
- H01L27/118
- H01L27/146
- H01L29/06
- H01L29/423
- H01L21/311
- H01L29/66
- H01L27/12
- H01L29/786
- H01L21/3213
- H01L29/78
- H01L21/425
- H01L29/24
- H10B61/00
- H10B63/00
- H01L29/51
- H01L31/119
- H01L31/0224
- H03K3/012
- H03K17/56
- H03K3/017
- H03K5/02
- H03K5/156
- H03L7/107
- H05K1/18
- H01L27/11
- G11C11/412
- H01L27/105
- H01L27/11507
- H10B53/30
- H10B53/10
- H01F10/32
- H01F41/32
- G11C11/16
- H10N50/01
- H10N50/80
- H01L45/00
- H01L27/24
- H10N70/00
- H10N70/20
