TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on March 28th, 2024
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on March 28th, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 75 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (27), H01L21/8234 (20), H01L29/06 (17), H01L27/088 (16), H01L29/66545 (15)
With keywords such as: layer, semiconductor, structure, gate, substrate, device, region, dielectric, forming, and fin in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Chun-Yi CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Piao CHUU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Miin-Jang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/455, C23C16/40, C23C16/44, C23C16/505, C23C16/56
Abstract: a method includes following steps. a first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. a first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. a second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. the material is then removed using a plasma. the substrate is biased during removing the material.
Inventor(s): Tung-Tsun CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsing HSIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jie HUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N27/414, G01N33/569, H01L21/762
Abstract: an ic structure includes a biologically sensitive field-effect transistor (biobet) in a semiconductor substrate, and a dielectric layer over a backside surface of the semiconductor substrate. the dielectric layer has a sensing well extending through the dielectric layer to a channel region of the biofet. the ic structure further includes a biosensing film, a plurality of fluid channel walls, and a first heater. the biosensing film lines the sensing well in the dielectric layer. the fluid channel walls are over the biosensing film and define a fluid containment region over the sensing well of the dielectric layer. the first heater is in the semiconductor substrate. the first heater has at least a portion overlapping with the fluid containment region.
Inventor(s): Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Yu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng Tai of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/122, G02B6/13
Abstract: optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. the evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Hui Huang of Dongshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Yun Hou of Jubei (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsi Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/122
Abstract: a device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
Inventor(s): Chih-Wei Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taioei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
Abstract: a method includes forming an optical engine, which includes a photonic die. the photonic die further includes a grating coupler. the method further includes forming a fiber unit including a fiber platform having a groove, and an optical fiber attached to the fiber platform. the optical fiber extends into the groove. the fiber platform further includes a reflector. the fiber unit is attached to the optical engine, and the reflector is configured to deflect a light beam, so that the light beam emitted by a first one of the optical fiber and the grating coupler is received by a second one of the optical fiber and the grating coupler.
Inventor(s): Chue San YOO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Yue LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/64, G03F1/62
Abstract: a system includes a mask. the system further includes a pellicle frame attached to the mask. the pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from a first side of the pellicle from to a second side of the pellicle frame. the pellicle frame further includes a flat bottom surface having only a single recess therein, wherein the flat bottom surface is free of an adhesive. the system further includes a gasket within the single recess.
Inventor(s): Xianhui ZHOU of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Lei WANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Zihao ZHANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Huiming XU of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/84
Abstract: a reticle inspection and purging method comprises following steps. a first reticle is moved from a first load port of a lithography tool to a reticle inspection tool located outside the lithography tool. the first reticle is inspected using the reticle inspection tool located outside the lithography tool. whether the first reticle is acceptable for exposure is determined based on the inspection result. in response the determination determines that the first reticle is not acceptable for exposure, the first reticle is purged.
Inventor(s): Chun-Chih HO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/36, H01L21/027
Abstract: a method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. in some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. in yet some embodiments, the molding layer has a glass transition temperature that is 3� c.-30� c. less than the glass transition temperature of the patterned photoresist.
Inventor(s): Tai-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jung PAN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Hung CHEN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Kang YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
Abstract: the present disclosure provides an extreme ultraviolet (euv) lithography system including a radiation source and an euv control system integrated with the radiation source. the euv control system includes a 3-dimensional diagnostic module (3ddm) designed to collect a laser beam profile of a laser beam from the radiation source in a 3-dimensional (3d) mode, an analysis module designed to analyze the laser beam profile, a database designed to store the laser beam profile, and an euv control module designed to adjust the radiation source. the analysis module is coupled with the database and the euv control module. the database is coupled with the 3ddm and the analysis module. the euv control module is coupled with the analysis module and the radiation source.
Inventor(s): Yi-Lin CHUANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Wen TAN of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Song LIU of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Shih-Yao LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Yuan FANG of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/373, G06F30/394, G06F30/398
Abstract: a method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. the macros have multiple pins coupled to the channels interposed between the macros.
Inventor(s): Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Charles Chew-Yuen YOUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shun Li CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/39, G06F30/394, H01L27/02, H01L27/118
Abstract: a system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. the processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. the generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. the cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
Inventor(s): Chih-Yu Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsin Nien of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hidehiro Fujiwara of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei Chen of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/12, G11C7/18, G11C7/22
Abstract: disclosed herein are related to a memory device. in one aspect, a memory device includes a set of memory cells. in one aspect, the memory device includes a first bit line extending along a direction. the first bit line may be coupled to a subset of the set of memory cells disposed along the direction. in one aspect, the memory device includes a second bit line extending along the direction. in one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.
Inventor(s): Ming-Yen CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/406, G11C11/4091, G11C11/4096
Abstract: an integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. the integrated circuit also includes a read-write driver which is connected to the set of data lines and is configured to receive a flip-refresh control signal. the read-write driver has a catch circuit configured to store a first bit value related to a stored bit value in a selected memory cell. the read-write driver is configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/412, G11C11/417, H10B10/00
Abstract: a semiconductor device includes first and second active areas, first and second gate structures, and first to third conductive segments. the first and second active areas extend along the first direction. the first and second gate structures cross over the first and second active areas. the first conductive segment crosses over the first and second gate structures, stores a first data signal, and is coupled to the first gate structure, the first and second active areas. the second conductive segment crosses over the first and second gate structures, stores a first complementary data signal, and is coupled to the second gate structure, the first and second active areas. the third conductive segment crosses over the first and second gate structures, and is coupled to the second active area. the first to third conductive segments are arranged in order along a second direction different from the first direction.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/412, H01L23/48, H10B10/00
Abstract: a method for forming a memory device includes forming a first pull-up transistor, a first pull-down transistor, a first pass-gate transistor, a second pull-up transistor, a second pull-down transistor, a second pass-gate transistor over a substrate; forming a first bit line and a second bit line electrically connected to a source/drain epitaxy structure of the first pass-gate transistor and a source/drain epitaxy structure of the second pass-gate transistor; forming a word line electrically connected to gate structures of the first and second pass-gate transistors; removing the substrate to expose a source/drain epitaxy structure of the first pull-down transistor and a source/drain epitaxy structure of the second pull-down transistor; and forming a first power line electrically connected to the bottom surface of the source/drain epitaxy structure of the first pull-down transistor and electrically connected to the bottom surface of the source/drain epitaxy structure of the second pull-down transistor.
Inventor(s): Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Sheng Yun of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Tse HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Ming YU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Zhan Li of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/285, H01L21/28, H01L21/3105, H01L29/51, H01L29/786
Abstract: a method for manufacturing a semiconductor device is described. the method includes the following steps. a low-dimensional material (ldm) layer is formed on a semiconductor substrate, wherein the ldm layer includes sublayers stacked upon one another. a plasma treatment is performed to the ldm layer to transform at least one sublayer into an oxide layer, wherein the plasma treatment is performed under a temperature equivalent to or lower than about 80 degrees celsius. at least one electrode is disposed over the oxide layer.
Inventor(s): Che-Hao Tu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., William Weilun Hong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Tsung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3105, H01L21/306, H01L21/8234
Abstract: a method of removing a hard mask is provided. gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. a dielectric layer is deposited on the substrate and on the patterned gate stacks. a first portion of the dielectric layer is planarized by chemical mechanical polishing (cmp) to remove a topography of the dielectric layer. the hard mask and a second portion of the dielectric layer are removed by the cmp.
Inventor(s): Yi-Hsiu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kenichi SANO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/311, H01L21/02
Abstract: a selective etching process includes treating a first dielectric region and a second dielectric region of a semiconductor device with a self-assembled-monolayer-forming compound to form a self-assembled monolayer to selectively cover the first dielectric region so as to expose the second dielectric region; and selectively etching the second dielectric region using a dilute acid solution while the first dielectric region is protected by the self-assembled monolayer from being etched by the dilute acid solution.
Inventor(s): Kenichi Sano of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Kai Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/768, H01L21/8238, H01L27/088
Abstract: the present disclosure provides a method for repairing a seam within a conformally deposited material. one or more seam repairing precursor sources may be delivered to seams or voids using a carrier at a super critical fluid phase. at the super critical fluid phase, the carrier has liquid like density and gas like high diffusion capability, therefore capable of delivering the repairing precursor sources to seams or voids under surfaces of a structure. in some embodiments, carbon dioxide or argon may be used as a carrier.
Inventor(s): Chao-Ching Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Ang Chao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lain-Jong Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L29/06, H01L29/24, H01L29/423, H01L29/66, H01L29/786, H10K10/46, H10K71/12, H10K85/20
Abstract: a method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. a transistor is then formed based on the protruding fin.
Inventor(s): Yu-Lien Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/08, H01L29/417, H01L29/66, H01L29/78
Abstract: a method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. a spacer layer is formed over the dummy gate structure and the fins. the spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. a source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. a device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. an epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.
Inventor(s): Xusheng Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Keung Leung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huiling Shang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/78, H01L29/786
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (s/d) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk s/d feature is separated from the substrate by a first air gap, and the bulk s/d feature is separated from the inner spacers by second air gaps.
Inventor(s): Chin-Ta CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Wei WU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Hsiang LUNG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Tai LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/308, H01L27/088
Abstract: a first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. a second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.
Inventor(s): Ka-Hing Fung of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/306, H01L29/06, H01L29/423, H01L29/66, H01L29/786
Abstract: an embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate.
Inventor(s): Da-Zhi ZHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Pin HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Nien CHEN of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Han LIU of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yung LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088
Abstract: a method for forming a semiconductor device structure is provided. the method includes providing a substrate having a base, a first fin, and a second fin over the base. the method includes forming a first trench in the base and between the first fin and the second fin. the method includes forming an isolation layer over the base and in the first trench. the first fin and the second fin are partially in the isolation layer. the method includes forming a first gate stack over the first fin and the isolation layer. the method includes forming a second gate stack over the second fin and the isolation layer. the method includes removing a bottom portion of the base. the isolation layer passes through the base after the bottom portion of the base is removed.
Inventor(s): Wensen Hung of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/10, H01L23/00, H01L23/36, H01L23/42, H01L25/00, H01L25/18
Abstract: in an embodiment, a device includes: an integrated circuit package including: a package component; and a package stiffener attached to the package component; and a heat spreader attached to the integrated circuit package, a main portion of the heat spreader disposed above the package stiffener, a protruding portion of the heat spreader extending through the package stiffener; an elastic adhesive material between the main portion of the heat spreader and the package stiffener; and a thermal interface material between the protruding portion of the heat spreader and the package component, the thermal interface material different from the elastic adhesive material.
Inventor(s): Satyabrata DASH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Sing LI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/8234, H01L27/088, H01L29/66, H01L29/78
Abstract: a semiconductor device includes first and second gate structures, a metallization layer, and first and second tie-off contacts. the first and second gate structures extend substantially along a first direction and are aligned with each other substantially along the first direction. the metallization layer includes a vdd line, a vss line, metal lines between the vdd line and the vss line and extending substantially along a second direction different from the first direction. the first tie-off contact overlaps an intersection of the first gate structure and a first one of the vdd line and the vss line from a top view. the second tie-off contact overlaps an intersection of the second gate structure and a first one of the metal lines from the top view, wherein said first one of the metal lines is adjacent to a second one of the vdd line and the vss line.
Inventor(s): Chia Chen LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
Abstract: an interconnect structure and methods of forming the same are described. in some embodiments, the structure includes a first dielectric layer disposed over a substrate, a second dielectric layer disposed over the first dielectric layer, and a first conductive feature disposed in the second dielectric layer. the first conductive feature has a first top critical dimension and a first height. the structure further includes a second conductive feature disposed in the first and second dielectric layers. the second conductive feature has a second top critical dimension substantially greater than the first top critical dimension and a second height substantially greater than the first height.
Inventor(s): Wei-An LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Te-Hsin CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
Abstract: an integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. the integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. the first active device has an output coupled to a first layer deep line that is in the low resistivity portion. the second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. the low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.
Inventor(s): Fong-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Noor Mohamed Ettuveettil of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Bor Jan of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chou Liu of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Kan Cheng of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/00, H01L23/522
Abstract: semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. a signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. a signal external connection is electrically connected to the signal pad.
Inventor(s): Shang-Yun Hou of Jubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Pin Hu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/31, H01L23/498
Abstract: semiconductor devices and methods of manufacture are provided. in embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
Inventor(s): Chen-Hsuan Tsai of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chuan Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Fu Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L23/522, H01L25/00, H01L25/065
Abstract: a semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. the second semiconductor die is disposed beside the first semiconductor die. the semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. the integrated passive device is electrically connected to the first semiconductor die. the first redistribution layer is disposed over the semiconductor bridge. the connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. the first redistribution layer is interposed between the integrated passive device and the connective terminals.
Inventor(s): Jeng-An Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chi Lin of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Cheng Hou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31
Abstract: embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. a buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. after the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.
Inventor(s): Hsien-Pin Hu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jing-Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Ren Lai of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/56, H01L21/683, H01L23/00, H01L23/14, H01L23/31, H01L23/498
Abstract: a device includes an interposer, which includes a substrate having a top surface. an interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. a plurality of through-substrate vias (tsvs) is in the substrate and electrically coupled to the interconnect structure. a first die is over and bonded onto the interposer. a second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
Inventor(s): Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yu Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shen Cheng of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang Tsao of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Jui Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Shiuan Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/498
Abstract: a method of manufacturing a package structure at least includes the following steps. an encapsulant laterally is formed to encapsulate the die and the plurality of through vias. a plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. a warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. a protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. a coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
Inventor(s): Tsung-Hao YEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien Hung LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsien Jung CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Heng WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/60, H01L21/768, H01L23/00, H01L23/48, H01L25/065
Abstract: a semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (wow) configuration. a through silicon via (tsv) structure may be formed through the device region. the high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. in particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the tsv structure. accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
Inventor(s): Chita CHUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Chun CHUANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Shu LIN of Yonghe City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Cheng KUO of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
Abstract: a method of making a semiconductor device includes patterning a conductive layer over a substrate to define a conductive pad having a first width. the method includes depositing a passivation layer, wherein the passivation layer directly contacts the conductive pad. the method includes depositing a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. the method includes depositing an under-bump metallization (ubm) layer directly contacting the conductive pad, wherein the ubm layer has a second width greater than the first width. the method includes depositing a mask layer over the ubm layer; and forming an opening in the mask layer wherein the opening has the second width. the method includes forming a conductive pillar in the opening on the ubm layer; and etching the ubm layer using the conductive pillar as a mask, wherein the etched ubm layer has the second width.
Inventor(s): Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/56, H01L23/00, H01L23/31, H01L23/498
Abstract: a package structure and methods for forming the package structure are provided. the package structure includes a package component, an encapsulant disposed around the package component, and a redistribution structure disposed over the package component and the encapsulant. the package component includes a substrate, a protection structure, which includes an organic material, over a first surface of the substrate, and a multi-layered structure encapsulated by the protection structure. sidewalls of the multi-layered structure are spaced apart from the encapsulant by the protection structure.
Inventor(s): Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Techi Wong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Wei Chou of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/56, H01L23/00, H01L23/31
Abstract: structures and methods of forming fan-out packages are provided. the packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. embodiments include a cavity preformed in a cavity substrate. various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. redistribution structures may also be formed.
Inventor(s): Fu-Chiang Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meei-Shiou Chern of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Ting Hou of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/01, H01L21/762, H01L21/84
Abstract: semiconductor structures and methods are provided. an exemplary method according to the present disclosure includes forming a trench extending into a substrate, in a top view, the trench extends lengthwise along a first direction, forming a material layer over the substrate and intersecting a first portion of the trench, after the forming of material layer, forming a first capacitor intersecting a second portion of the trench, the first capacitor comprising a first plurality of conductor plates, and forming a second capacitor intersecting a third portion of the trench, the second capacitor comprising a second plurality of conductor plates, where the first plurality of conductor plates and the second plurality of conductor plates are in direct contact with the material layer.
Inventor(s): Kuo-Cheng Ching of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/033, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
Abstract: examples of an integrated circuit with finfet devices and a method for forming the integrated circuit are provided herein. in some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. the gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. in some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor device is provided. the semiconductor includes a plurality of semiconductor components and at least two dielectric walls disposed among the semiconductor components. two of the dielectric walls, which are adjacent, extended along one direction or disposed at two sides of a device isolation, have varied wall widths or offset.
Inventor(s): Gerben Doornbos of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Marcus Johannes Henricus Van Dal of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/78
Abstract: an integrated circuit includes a complimentary field effect transistor (cfet). the cfet includes a first transistor and a second transistor stacked vertically. a conductive via extends vertically from a first source/drain region of the first transistor past the second transistor. the second transistor includes an asymmetric second source/drain region. the asymmetry of the second source/drain region helps ensure that the second source/drain region does not contact the conductive via.
20240105726.TIE OFF DEVICE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Shao-Lun Chien of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Wei Chiang of New Taipei city (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong Zhuang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Dai Sue of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/765, H01L21/8234, H01L21/8238, H01L23/522, H01L23/528, H01L27/088
Abstract: an integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. a first transistor includes the first active area and a first one of the gates. the first transistor has a first threshold voltage (vt). a second transistor includes the first active area and a second one of the gates. the second transistor has a second vt different than the first vt. a tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
20240105750.CMOS IMAGE SENSOR_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Ming-Hsien YANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao Chou of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Lee of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: a cmos image sensor includes pdaf pixels distributed in an array of image pixels in plan view. each pdaf pixel includes m�m binned photodiodes, a pdaf color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a pdaf micro-lens overlying the pdaf color filter. a first horizontal distance between a center of the pdaf color filter and a center of the binned photodiodes varies depending on a location of the pdaf pixel in plan view in the cmos image sensor. additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. the second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. thus, quantum efficiency and uniformity of the cmos image sensor are improved.
Inventor(s): Chung-Lei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Anhao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L21/033, H01L21/266, H01L21/3065
Abstract: a semiconductor device includes a substrate having a first device and a second device, where at least one of the first device and the second device includes a photo-sensitive element. the semiconductor device includes a first isolation feature surrounding the first device, where the first isolation feature has a first depth. the semiconductor device includes a second isolation feature surrounding the second device, where the second isolation feature has a second depth and where the first depth is greater than the second depth.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
Abstract: a device includes a substrate, a first nanostructure device, a second nanostructure device, a dielectric fin, an isolation structure, and first and second dielectric gate structures. the substrate has a first device region, a second device region, and a connecting region. the first nanostructure device is over the first device region. the second nanostructure device is over the second device region. the dielectric fin is over the first device region and the connecting region and is in contact with a gate structure of the first nanostructure device. the isolation structure is over the second device region and is in contact with the second nanostructure device and the dielectric fin. the first dielectric gate structure is over the substrate and between the first device region and the connecting region. the second dielectric gate structure is over the substrate and between the second device region and the connecting region.
Inventor(s): Chung-Yu CHIANG of Yuanlin Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Han LIU of Gongguan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Hung TSENG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yung LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8234, H01L29/66
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. the method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. the method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. a first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
Inventor(s): I-Sheng CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia YEO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Chieh YEH of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsien WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/10, H01L21/8238, H01L27/088, H01L27/092, H01L29/06, H01L29/165, H01L29/423, H01L29/66, H01L29/78, H01L29/786
Abstract: a semiconductor device includes a fin extending from a substrate. the fin has a source/drain region and a channel region. the channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. a high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. a metal layer is formed along opposing sidewalls of the high-k dielectric layer. the metal layer includes a first material. the spacing area is free of the first material.
Inventor(s): Shih-Yen LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Jia CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/16, H01L21/02, H01L21/8234, H01L27/088, H01L29/66
Abstract: a method includes performing a first deposition process to form a first graphene layer over a substrate, the first deposition process being performed under a first temperature and a first pressure; performing a second deposition process to form a second graphene layer over the first graphene layer, the second deposition process being performed under a second temperature and a second pressure, in which the first temperature is higher than the second temperature, and the first pressure is lower than the second pressure; forming a gate structure over the second graphene layer; and forming source/drain contacts on opposite sides of the gate structure and electrically connected to the first and second graphene layers.
Inventor(s): Chun-Sheng LIANG of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Chih CHEN of Changhua (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/06, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a first source/drain (s/d) region disposed over a substrate, a second s/d region disposed over the substrate, a dielectric wall disposed between the first and second s/d regions, a first conductive contact disposed over and electrically connected to the first s/d region, a second conductive contact disposed over and electrically connected to the second s/d region, and a first dielectric material in contact with the dielectric wall. the first dielectric material has a top surface located at a first level between a top surface of the first conductive contact and a bottom surface of the first conductive contact, and the first dielectric material extends from the first level to a second level located below the bottom surface of the first conductive contact.
Inventor(s): Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yueh-Ching PAI of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/285, H01L21/311, H01L29/06, H01L29/08, H01L29/423, H01L29/45, H01L29/66, H01L29/775
Abstract: embodiments of the present disclosure provide a method of forming a contact opening using selective ale operations to remove ild layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.
Inventor(s): Pei-Yu WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/417, H01L29/66, H01L29/775, H01L29/786
Abstract: an integrated circuit includes a semiconductor nanostructure transistor. the semiconductor nanostructure transistor includes a plurality of semiconductor nanostructures corresponding to channel regions conductor nanostructure transistor. a gate metal surrounds the semiconductor nanostructures. the gate metal has differing gate length dimension above the semiconductor nanostructures compared to the gate length between the semiconductor nanostructures.
Inventor(s): Jun-Ye Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jih-Sheng Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsien Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/28, H01L29/49, H01L29/66, H01L29/78
Abstract: a method for fabricating semiconductor devices is disclosed. the method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. the method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. the method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. the metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. the gate electrode has an upper surface extending away from a top surface of the metal gate structure.
Inventor(s): Chun-Sheng LIANG of PuyanTownship (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Chih CHEN of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao CHANG of Hsin-chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/08, H01L29/786
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. the semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. the second direction is different from the first direction. in addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. the semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.
Inventor(s): Che-Lun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting Pan of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/66, H01L29/775, H01L29/786
Abstract: semiconductor structures and methods of forming the same are provided. in an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature coupled to the vertical stack of channel members and adjacent the gate structure; and a dielectric feature disposed between the source/drain feature and the substrate, in a cross-sectional view, the dielectric feature includes a v-shape sidewall surface.
Inventor(s): Hsueh Wen Tsau of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Ziwei Fang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Liang Sung of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/56, H01L21/82, H01L23/28, H01L29/78
Abstract: a semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. the metal oxide layer and the interfacial layer form a dipole moment. the metal oxide layer includes a first metal. the metal halide layer includes a second metal different from the first metal.
Inventor(s): Che-Lun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Ming Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ji-Yin Tsai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/306, H01L21/8234, H01L29/06, H01L29/423, H01L29/49, H01L29/786
Abstract: a first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. the first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. the second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. a source/drain trench is formed in a region of the stack to expose side surfaces of the layers. a first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. a spacer is formed in the gap. a source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.
Inventor(s): Yi-He Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Long-Jie Hong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L23/528, H01L29/78
Abstract: a semiconductor device includes a semiconductor channel. the semiconductor device includes a metal gate structure disposed over the semiconductor channel. the semiconductor device includes a gate electrode having a bottom surface contacting an upper surface of the metal gate structure. the gate electrode has its side portions extending from its top surface toward the semiconductor fin with a first depth and a central portion extending from its top surface toward the semiconductor fin with a second depth, the first depth being substantially greater than the second depth.
Inventor(s): Jian-Jou Lian of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Neng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsi Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Wei Chen of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Ang Chiang of I-lan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/84, H01L29/78
Abstract: a semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. a lower portion of the gate electrode is between the first spacers. an upper portion of the gate electrode is above the first spacers. the second spacers are adjacent the first spacers opposite the gate electrode. the upper portion of the gate electrode is between the second spacers.
Inventor(s): Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Pang-Yen TSAI of Jhu-bei City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu LIN of Ping-Tung (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li WANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/423, H01L29/66
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. the semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. the epitaxial structures include a second semiconductor material that is different than the first semiconductor material. the semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.
Inventor(s): Da-Zhi ZHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-An LU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yu CHIANG of Yuanlin Township (TW) for taiwan semiconductor manufacturing company, ltd., Po-Nien CHEN of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Han LIU of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yung LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L23/522, H01L23/528, H01L29/66
Abstract: a method for forming a semiconductor structure is provided. the method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. the fin structure is cut into two segments by the trench. a first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.
Inventor(s): Che-Yu Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Chieh Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/311, H01L21/8234, H01L27/088, H01L29/08, H01L29/51, H01L29/66
Abstract: semiconductor device and the manufacturing method thereof are disclosed herein. an exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.
Inventor(s): Jiefeng Jeff LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua TSAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shyh-Horng YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/265, H01L21/266, H01L29/66
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a first well region and a second well region in a substrate. the method includes forming a third well region in the substrate and between the first well region and the second well region. the method includes forming a deep well region in the substrate and under the first well region and the third well region. the method includes partially removing the substrate to form a first fin, a second fin, and a third fin in the first well region, the second well region, and the third well region respectively. the method includes forming a first epitaxial structure, a second epitaxial structure, and a third epitaxial structure in the first recess, the second recess, and the third recess respectively.
Inventor(s): Jhy-Jyi Sze of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Sin-Yi Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Shin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yin-Kai Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Lin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L31/112, H01L27/146, H01L29/66, H01L29/808, H01L31/18
Abstract: germanium-based sensors are disclosed herein. an exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (jfet) formed from a germanium layer disposed on and/or in a silicon substrate. a doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. in embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. the jfet has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. in some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. in some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Jung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L33/62, H01L23/522, H01L25/075, H01L33/10, H01L33/46, H01L33/52
Abstract: in an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.
Inventor(s): Yu-Hung YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wun-Jie LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wem LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02H3/08, H02H1/00
Abstract: an electrostatic discharge (esd) protection circuit includes a first and second diode in a semiconductor wafer, an esd clamp circuit and a first conductive structure on a backside of a semiconductor wafer. the first diode is coupled between an input output (io) pad and a first node. the second diode is coupled to the first diode, and coupled between the io pad and a second node. the esd clamp circuit is in the semiconductor wafer, coupled to the first and second node, and between the first and second diode. the esd clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a reference voltage supply. the second diode is coupled to and configured to share the first signal tap region with the esd clamp circuit. the first conductive structure is configured to provide a reference voltage to the first signal tap region.
Inventor(s): Chung-Peng HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chow PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K5/14, H03K5/131, H03K5/134, H03K5/24
Abstract: a delay-locked loop (dll) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (dcdl) coupled to the low pass filter. the dcdl includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.
Inventor(s): Chi-Wei Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Che Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Ya Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/78
Abstract: an ic structure and a method of forming the same are provided. in an embodiment, an exemplary method of forming the ic structure forming a first semiconductor fin and a second semiconductor fin protruding from a substrate, forming a high-k metal gate (hkmg) structure over the first semiconductor fin and the second semiconductor fin, forming a trench to separate the hkmg structure into two portions, conformally depositing a first dielectric layer in the trench, depositing a second dielectric layer over the first dielectric layer to fill the trench, wherein the second dielectric layer includes nitrogen, and the first dielectric layer is free of nitrogen, and planarizing the first dielectric layer and second dielectric layer to form a gate isolation structure in the trench.
Inventor(s): Chin-Shan WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shun-Yi LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B12/00
Abstract: a method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. the method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. the method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode, and the insulating layer extends above a top-most surface of the substrate.
Inventor(s): Shih-Hsien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yao Ko of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Felix Ying-Kit Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B41/35, G11C16/10, H01L29/06, H01L29/66, H01L29/788, H10B41/41, H10B41/42
Abstract: various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. a conductive structure overlies the first well region. a pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. the pair of first doped regions comprise a second doping type opposite the first doping type. a pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. the pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.
Inventor(s): Chun-Chieh LU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chuan SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Ying HUANG of Jhonghe City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30, G11C5/06, H01L21/02, H01L29/06
Abstract: an antiferroelectric field effect transistor (anti-fefet) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. the antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. this enables the antiferroelectric layer in the fefet to provide a sharper/larger voltage drop for an erase operation of the fefet (e.g., in which the fefet switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.
Inventor(s): Chih-Wei WU of Zhuangwei Township (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih CHIOU of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih SU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Nan YUAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B80/00, H01L23/00, H01L23/29, H01L23/31, H01L23/48
Abstract: a system on chip (soc) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the soc die package is above a top surface of an adjacent memory die package. this may be achieved through the use of various attachment structures that increase the height of the soc die package. after encapsulating the memory die package and the soc die package in an encapsulation layer, the encapsulation layer is grinded down. the top surface of the soc die package being above the top surface of the adjacent memory die package results in the top surface of the soc die package being exposed through the encapsulation layer after the grinding operation. this enables heat to be dissipated through the top surface of the soc die package.
Inventor(s): Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B80/00, H01L23/00, H01L23/48, H01S5/02315, H01S5/0232, H01S5/02345, H01S5/028
Abstract: optical devices and methods of manufacture are presented in which an opening is formed within a first semiconductor device and then bonded to other optical devices. a laser die or other fill material may be used to refill the opening. the first semiconductor device is then electrically connected to an optical interposer.
Inventor(s): Shih-Yen LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Cheng TSAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H10B63/00
Abstract: a memory device includes a substrate, a 2-d material channel layer, a 2-d material charge storage layer, source/drain contacts, a gate dielectric layer, and a gate electrode. the 2-d material channel layer is over the substrate. the 2-d material charge storage layer is over the 2-d material channel layer. the 2-d charge storage layer and the 2-d material channel layer include the same chalcogen atoms. the source/drain contacts are over the 2-d material channel layer. the gate dielectric layer covers the source/drain contacts and the 2-d material charge storage layer. the gate electrode is over the gate dielectric layer.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on March 28th, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- C23C16/455
- C23C16/40
- C23C16/44
- C23C16/505
- C23C16/56
- Taiwan semiconductor manufacturing company, ltd.
- G01N27/414
- G01N33/569
- H01L21/762
- G02B6/122
- G02B6/13
- G02B6/42
- G03F1/64
- G03F1/62
- G03F1/84
- G03F7/36
- H01L21/027
- G03F7/00
- G06F30/392
- G06F30/373
- G06F30/394
- G06F30/398
- G06F30/39
- H01L27/02
- H01L27/118
- G11C7/12
- G11C7/18
- G11C7/22
- G11C11/406
- G11C11/4091
- G11C11/4096
- G11C11/412
- G11C11/417
- H10B10/00
- H01L23/48
- H01L21/285
- H01L21/28
- H01L21/3105
- H01L29/51
- H01L29/786
- H01L21/306
- H01L21/8234
- H01L21/311
- H01L21/02
- H01L21/768
- H01L21/8238
- H01L27/088
- H01L29/06
- H01L29/24
- H01L29/423
- H01L29/66
- H10K10/46
- H10K71/12
- H10K85/20
- H01L29/08
- H01L29/417
- H01L29/78
- H01L21/308
- H01L23/10
- H01L23/00
- H01L23/36
- H01L23/42
- H01L25/00
- H01L25/18
- H01L23/522
- H01L23/528
- H01L23/538
- H01L21/48
- H01L21/56
- H01L23/31
- H01L23/498
- H01L25/065
- H01L21/683
- H01L23/14
- H01L23/60
- H01L27/01
- H01L21/84
- H01L21/033
- H01L27/092
- H01L29/775
- H01L21/765
- H01L27/146
- H01L21/266
- H01L21/3065
- H01L29/10
- H01L29/165
- H01L29/16
- H01L29/45
- H01L29/49
- H01L21/82
- H01L23/28
- H01L21/265
- H01L31/112
- H01L29/808
- H01L31/18
- H01L33/62
- H01L25/075
- H01L33/10
- H01L33/46
- H01L33/52
- H02H3/08
- H02H1/00
- H03K5/14
- H03K5/131
- H03K5/134
- H03K5/24
- H10B12/00
- H10B41/35
- G11C16/10
- H01L29/788
- H10B41/41
- H10B41/42
- H10B51/30
- G11C5/06
- H10B80/00
- H01L23/29
- H01S5/02315
- H01S5/0232
- H01S5/02345
- H01S5/028
- H10N70/00
- H10B63/00
- H01L29/66545
