TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on February 15th, 2024
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on February 15th, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 59 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (20), H01L29/775 (19), H01L29/06 (14), H01L29/423 (11), H01L29/0673 (10)
With keywords such as: structure, layer, gate, semiconductor, disposed, device, substrate, memory, forming, and contact in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Yen-Hao LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Han TSAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chueh-Chi KUO of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B08B3/02, B08B1/00, B08B5/02, B08B5/04, B24B7/22
Abstract: a cleaning device for cleaning particles from a tool includes a nozzle structure having a spray opening to spray a cleaning liquid in a first direction to the tool, a cleaning pad disposed around the nozzle structure, and a support disposed around the cleaning pad. the cleaning pad exposes the spray opening and includes a front surface facing in the first direction to clean the tool. the support includes multiple gas openings to blow a pressurized gas in the first direction to the tool, and multiple vacuum openings to suck residual gas, liquid and particles around the tool. an air wall around the tool is thus generated by a combination of operations performed by the multiple gas openings and the multiple vacuum openings to reduce or prevent contamination that might be caused by the cleaning device in the chamber.
Inventor(s): Chih-Wen Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yeo-Sin Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Wei Hsu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hao Tu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi Huang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kei-Wei Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B08B3/10, B08B1/00, B24B37/04, B24B37/10, B24B37/30, B24B57/02
Abstract: a process tool including a polishing pad on a top surface of a wafer platen. a wafer carrier is configured to hold a wafer over the polishing pad. a slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. a first conductive rod is within the wafer platen and coupled to a first voltage supply. a wafer roller is configured to support the wafer. a first wafer brush is arranged beside the wafer roller. a second conductive rod is within the first wafer brush and coupled to a second voltage supply. the first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. the second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.
Inventor(s): Jun-Nan NIAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chih TSAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B24B49/00, H01L21/304, H01L21/67
Abstract: an apparatus for monitoring a cmp process on a wafer includes vibration sensors to collect vibration data corresponding to the cmp process and to transmit electric signals, a signal processor to obtain digital signals by converting the electric signals into a frequency domain, and filters to filter out noise signals from the digital signals to obtain noise reduced digital signals. the signal processor obtains one or more frequency spectrums from the noise reduced digital signals, and determines a micro-scratch occurrence on the wafer by analyzing the obtained one or more frequency spectrums. the vibration sensors are in rigid contact with at least a tool such as a head holding a carrier of the wafer or a platen holding a polishing pad. each vibration sensor includes at least two sub-frequency-ranges respectively corresponding to at least two materials to be polished by the polishing pad.
Inventor(s): Wen-Chang HSUEH of Longtan Township (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Cyonglin Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24
Abstract: a reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a first absorber layer disposed on the capping layer, a first multilayer disposed over the first absorber layer, a second absorber layer disposed on the first multilayer layer, and a second multilayer, which is an uppermost layer of the reflective mask, disposed over the second absorber layer.
Inventor(s): Hsin-Chieh CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Che CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/42, G03F1/44
Abstract: in a layout alignment method of a lithographic system for semiconductor device processing, a reference pattern that is included in a reference pattern module is disposed over an alignment pattern of a substrate. the alignment pattern includes two or more sub-patterns that extend in a first interval along a first direction and are arranged with a first pitch in a second direction. each sub-pattern includes first patterns and second patterns. a width of the first pattern is at least twice as wide as a width of the second pattern. the reference pattern at least partially overlap with the alignment pattern. an overlay alignment error between the reference pattern and the alignment pattern of the substrate is determined. when the overlay alignment error is not more than a threshold value, a photo resist pattern is produced on the substrate based on the layout pattern associated with reference pattern.
Inventor(s): Chia Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Cheng CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Ling LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Hao HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/62
Abstract: a method includes performing a lithography process using a mask and a pellicle membrane; detaching the pellicle membrane from the mask after the lithography process is completed; performing an inspection process to the pellicle membrane, the inspection process including generating a laser beam toward the pellicle membrane from a laser source, such that the laser beam passes through the pellicle membrane; and generating an image by receiving the laser beam passing through the pellicle membrane using an image sensor; and determining whether a particle is present on the pellicle membrane or a pin hole is present in the pellicle membrane based on the image.
Inventor(s): Xiaoyu SUN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Murat Kerem AKARVARDAR of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F3/06, G06N3/0464
Abstract: a circuit includes a data buffer configured to sequentially output first and second pluralities of bits, a plurality of memory macros having a total number, and a distribution network coupled between the data buffer and the plurality of memory macros. the distribution network separates the first plurality of bits into the total number of first subsets, and outputs each first subset to a corresponding memory macro, and either outputs an entirety of the second plurality of bits to each memory macro, or separates the second plurality of bits into a number of second subsets less than or equal to the total number, and outputs each second subset to one or more corresponding memory macros. each memory macro outputs a product of the corresponding first subset and the one of the entirety of the second plurality of bits or the corresponding second subset of the second plurality of bits.
Inventor(s): Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsin Chu (TW) for taiwan semiconductor manufacturing company, ltd., Kam-Tou SIO of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C5/14, G11C5/06, H01L23/538, H01L23/50
Abstract: various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. in one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. the larger width(s) in turn increases the total area of the power stripe(s) to reduce the ir drop across the power stripe. the various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.
Inventor(s): Jui-Jen Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Chieh Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lun Lu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Win-San Khwa of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/08, G11C7/10
Abstract: the disclosure provides a method for controlling a sense amplifier. the control device includes a latch circuit and a control circuit. the latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. the control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.
Inventor(s): Ishan Khera of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Atul Katoch of Kanata (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G11C7/12, G11C7/08
Abstract: systems and methods are provided for a memory device including a first memory array, a local input/output (lio) circuit, and a global input/output (gio) circuit. the first memory array includes a memory cell and a local bit line. the lio circuit is configured to receive a local bit line signal on the local bit line and to generate a global bit line signal on a global bit line based on the local bit line signal. the gio circuit is coupled to the lio circuit and is configured to receive the global bit line signal. the gio circuit comprises a latch circuit including a global bit line signal latch that is configured to latch the global bit line signal, and a booster circuit that is configured to drive the global bit line signal in the gio circuit based on a previous global bit line signal.
Inventor(s): Mahmut Sinangil of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ting Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jonathan Tsung-Yung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C11/418
Abstract: a twelve-transistor (12t) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. the cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. various operations for the 12t memory cell, as well as circuitry to perform the operations, are disclosed.
Inventor(s): Han-Jong CHIA of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi YEONG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C14/00, G11C11/22, G11C11/419, H10B10/00, H10B51/30, H10B53/30
Abstract: memories are provided. a memory includes a plurality of ferroelectric random access memory (fram) cells arranged in a first memory array, a plurality of static random access memory (sram) cells arranged in a second memory array, and a controller configured to access the first memory array and the second memory array with different access rate. each of the fram cells includes a ferroelectric field-effect transistor (fefet). a gate structure of the fefet includes a gate electrode over a channel of the fefet, a ferroelectric layer over the gate electrode, a first electrode over the gate electrode, and a second electrode over the first electrode. the ferroelectric layer is formed between the first and second electrodes.
Inventor(s): Meng-Sheng Chang of Chu-bei City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/16, H10B20/25, H01L23/48, H01L29/06, H01L29/423
Abstract: a memory device includes a plurality of one-time-programmable (otp) memory cells formed as a memory array. each of the plurality of otp memory cells includes a transistor and a metal structure electrically coupled to each other in series, and the plurality of otp memory cells are formed on a first side of a substrate. the memory device includes a heater structure, disposed on a second side of the substrate opposite to the first side, that includes a plurality of interconnect structures. the plurality of interconnect structures are configured to conduct a substantially high current so as to elevate a temperature of the resistor when any of the otp memory cells is being programmed.
Inventor(s): Ted Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Saman Adham of Kanata (CA) for taiwan semiconductor manufacturing company, ltd., Marat Gershoig of Ottawa (CA) for taiwan semiconductor manufacturing company, ltd., Vineet Joshi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C29/36, G11C29/12, G11C29/44
Abstract: performing a built-in self-test (bist) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. the output data is generated by the memory macro in response to processing the at least one input vector. the bist also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.
Inventor(s): Peng-Soon LIM of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/02, H01L21/265
Abstract: a method for manufacturing a semiconductor device includes: depositing metal sputtered from a metal target on a semiconductor structure having a recess, so as to fill the recess; and oxidizing the metal on the semiconductor structure to turn the metal into dielectric.
20240055280.DE-TAPE TOOL_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chen Liang Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Kuo Hui Chang of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Ryder Su of Keelung (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Chun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67
Abstract: a method of removing a sacrificial substructure from a support structure is disclosed. the method includes receiving the support structure, where the support structure has the sacrificial substructure connected thereto, the sacrificial substructure having functioning electrical devices removed therefrom. the method also includes applying a barrier to the sacrificial substructure, puncturing the sacrificial substructure with a puncture plate to secure the sacrificial substructure to the puncture plate, and detaching the sacrificial substructure from the support structure by moving the puncture plate with respect to the support structure.
Inventor(s): Chia-Hsi Wang of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683, H01L21/66, H01L21/67
Abstract: various embodiments of the present application are directed toward an adjustable wafer chuck. the adjustable wafer chuck is configured to hold a wafer. the adjustable wafer chuck comprises a base portion and a pad portion. the base portion comprises a plurality of adjustable base structures. the pad portion is disposed on a first side of the base portion. the pad portion comprises a plurality of contact pads disposed on the plurality of adjustable base structures. each of the adjustable base structures are configured to move along a plane in a first direction and configured to move along the plane in a second direction that is opposite the first direction.
Inventor(s): Wei-Ting CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ju CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Shun CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Su-Hao LIU of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng CHANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/66
Abstract: a method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.
Inventor(s): Yueh-Ting Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Wei Tseng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Shih Yeh of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L23/498, H01L23/00, H01L21/463
Abstract: a semiconductor structure includes a package, an electrical device and an underfill material. the package includes a redistribution structure and at least one die, and the at least one die is disposed on a first side of the redistribution structure. the electrical device is disposed on a second side of the redistribution structure, the electrical device has a top surface and a bottom surface opposite to each other, and the top surface faces the redistribution structure. the underfill material is disposed between the top surface and the redistribution structure and extending toward the bottom surface, the underfill material has an end surface corresponding to the bottom surface, and the end surface is a flat surface. in addition, a manufacturing method of the semiconductor structure is also provided.
Inventor(s): Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/31, H01L25/065, H01L23/373, H01L25/00, H01L21/56, H01L23/00
Abstract: disclosed are a semiconductor package and a manufacturing method of a semiconductor package. in one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, one or more heat dissipation elements and an encapsulant. the plurality of semiconductor dies are disposed on the interposer substrate. the one or more heat dissipation elements are disposed on the plurality of semiconductor dies. the encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies and the one or more heat dissipation elements.
Inventor(s): Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L23/31, H01L23/498, H01L23/00, H01L21/48, H01L21/56
Abstract: a package includes a first molding compound layer, a conductive via embedded in the first molding compound layer, a semiconductor device, a redistribution structure and a second molding compound layer. the semiconductor device and the redistribution structure are respectively disposed on opposite sides of the first molding compound layer, wherein the semiconductor device is electrically connected to the redistribution structure through the conductive via. the second molding compound layer is disposed on the first molding compound layer, wherein the semiconductor device is encapsulated by the second molding compound layer.
Inventor(s): Shih-Wei Peng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng Tzeng of Hsin Chu (TW) for taiwan semiconductor manufacturing company, ltd., Kam-Tou Sio of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-An Lai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L23/528, H01L27/02, H01L27/06
Abstract: a monolithic three-dimensional (3d) integrated circuit (ic) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. the upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. a monolithic inter-tier via (miv) extends from the lower tier through the predetermined lateral space, and the miv has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.
Inventor(s): Cian-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Fu YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Pei LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Lung CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chi CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L23/528, H01L21/768
Abstract: a semiconductor device includes a dielectric structure, a conductive structure disposed in the dielectric structure, a first dielectric feature disposed over the dielectric structure, a conductive element disposed in the first dielectric feature and connected to the conductive structure, and a barrier feature disposed around the conductive element and disposed outside of the conductive structure.
Inventor(s): Yu-Sheng Lin of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Fu Kao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Lin Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Chun Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/15, H01L25/065
Abstract: a first integrated circuit (ic) die includes a first substrate. a second ic die includes a second substrate. at least one of the first substrate or the second substrate has a first surface orientation. the first ic die is spaced apart from the second ic die. a third die electrically interconnects the first ic die to the second ic die. the third die includes a third substrate having a second surface orientation. the second surface orientation is different from the first surface orientation.
Inventor(s): Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiung Wang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ta Hao Sung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Wei Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ping Wang of Hemei Township (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Wen Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Ta Lin of Gongguan Township (TW) for taiwan semiconductor manufacturing company, ltd., Li-Cheng Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Gao-Long Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/58, H01L23/48, H01L23/31, H01L21/56
Abstract: embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. the crack stopper structure may include multiple layers separated by a fill layer. the layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.
Inventor(s): Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/67, H01L21/02
Abstract: an integrated semiconductor packaging system includes: a first wet clean tool configured to perform a first wet clean process on a frame, wherein a plurality of top dies are disposed on the frame; a second wet clean tool configured to perform a second wet clean process on a wafer, wherein a plurality of bottom dies corresponding to the plurality of top dies, respectively, are disposed on the wafer; a pick-and-place tool configured to bond the plurality of top dies to the plurality of bottom dies, respectively; and a first transmission path through which the frame and the wafer are transferred from the first wet clean tool and the second wet clean tool to the pick-and-place tool, respectively, wherein the frame is directly transferred from the first wet clean tool to the pick-and-place tool, and the wafer is directly transferred from the second wet clean tool to the pick-and-place tool.
Inventor(s): JEN-YUAN CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/20, H01L23/24, H01L23/31, H01L25/00
Abstract: a method of manufacturing a semiconductor package includes: providing a substrate; providing a first die group comprising a first set of one or more dies, wherein the first die group is characterized by a first thickness; bonding a lower surface of the first die group to the substrate; providing a second die group comprising a second set of one or more dies, wherein the second die group is characterized by a second thickness larger than the first thickness; bonding the second die group to the substrate; providing a carrier substrate encapsulating at least one air gap, wherein the carrier substrate is characterized by a third thickness equal to or greater than a difference between the second thickness and the first thickness; and bonding a lower surface of the carrier substrate to an upper surface of the first die group.
Inventor(s): Chen-Hsuan TSAI of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Fu TSAI of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ting LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/48, H01L25/00, H01L23/00
Abstract: a package structure is provided. the package structure includes a substrate and a semiconductor chip over the substrate. the package structure also includes a protective frame laterally surrounding the semiconductor chip. the package structure further includes an underfill element between the semiconductor chip and the protective frame. a portion of the underfill element is directly below the protective frame.
Inventor(s): Chia-Chung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zi-Ang Su of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Ting Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Sheng Yuan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Kan Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01L29/06, H01L29/423, H01L29/775, H01L21/265, H01L29/66
Abstract: a semiconductor structure includes a substrate and a stack of p-n junction structures embedded in the substrate. the semiconductor structure includes a semiconductor fin protruding from the substrate. the semiconductor structure includes a pair of source/drain structures disposed in the semiconductor fin. the semiconductor structure includes a gate structure over a channel region of the semiconductor fin and interposed between the pair of source/drain structures.
Inventor(s): Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L29/06, H01L29/08, H01L29/10, H01L29/66
Abstract: a semiconductor device (having a cmos architecture) includes first to fourth cell regions each of the first and second cell regions includes a pair of first and second stacks of nanosheets relative to, e.g., the z-axis. the nanosheets of the first stack have a first dopant-type, e.g., n-type. the nanosheets of the second stack have a second dopant type, e.g., p-type. each pair of first and second stacks represents a cmos architecture relative to a second direction, e.g., the y-axis each of the third and fourth cell regions has cfet architecture, the cfet architecture being a type of cmos architecture relative to the z-axis. the third and fourth cell regions are adjacent each other relative to the y-axis. the first and second active regions are on corresponding first and second sides of each of the third and fourth active regions. the first and second cell regions are non-cfet cell regions.
Inventor(s): Chen-Hsiang HUNG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chuan TSENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hsin CHU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ping LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: a semiconductor device includes: a photodiode formed in a substrate; and at least one transistor having a gate feature that comprises a first portion and a second portion coupled to an end of the first portion, the first portion disposed above and extending along a major surface of the substrate and the second portion extending from the major surface of the substrate into the substrate, wherein the photodiode and the at least one transistor at least partially form a pixel.
Inventor(s): Yu-Wei HUANG of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsien LIN of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Hsuan HSU of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: an image sensor device and methods of forming an image sensor device are provided. the image sensor device includes a plurality of image-sensing elements arranged within the device substrate. the image sensor device further includes an isolation grid structure extending into the device substrate and made up of a plurality of isolation grid segments that surround the outer perimeters of the plurality of image-sensing elements. the isolation grid structure includes a passivation liner and a conductive material in contact with the passivation liner. the conductive material may be an indium-tin-oxide film.
Inventor(s): Fu-Chiang KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Han CHEN of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Wei LO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L49/02, H01L23/522, H01L29/66
Abstract: a method includes forming first-type deep trenches and second-type deep trenches in a substrate, in which the first-type deep trenches have a first lengthwise direction along a first direction and the second-type deep trenches have a second lengthwise direction along a second direction; forming a capacitor structure over the substrate and in the first-type deep trenches and the second-type deep trenches, in which the capacitor structure includes a first metallic electrode layer, a node dielectric layer over the first metallic electrode layer, and a second metallic electrode layer over the node dielectric layer; and forming a first metal via over the capacitor structure and in contact with the second metallic electrode layer of the capacitor structure, in which a length of the first metal via is greater than a width of the first metal via from a top view.
Inventor(s): Cheng-Wei Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. More of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Lun-Kuang Tan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu Chou of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yueh-Ching Pai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L27/092, H01L21/8238, H01L29/66, H01L29/423, H01L29/775, H01L29/786
Abstract: a method of fabricating a semiconductor device includes providing a dummy structure that includes channel layers, inner spacers disposed between adjacent ones of the channel layers, and a gate structure extending lengthwise in a first direction. a first trench extending lengthwise perpendicular to the first direction is formed, which divides the gate structure into segments. a first isolation feature is deposited in the first trench. the method also includes etching the gate structure and the channel layers to form a second trench extending lengthwise in the first direction. the second trench exposes the inner spacers. a second isolation feature is deposited in the second trench. the second isolation feature intersects the first isolation feature in a top view of the semiconductor device.
Inventor(s): Jung-Chien CHENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Lin CHEN of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/775, H01L29/66, H01L29/786, H01L21/8234
Abstract: a semiconductor device structure and a formation method are provided. the method includes forming a first fin structure and a second fin structure over a substrate. the method also includes forming a first metal gate stack wrapped around and extending across the first fin structure and the second fin structure. the method further includes forming a second metal gate stack wrapped around and extending across the first fin structure and the second fin structure. in addition, the method includes forming a protective structure extending into the first gate stack and forming a dielectric structure extending into the protective structure and the second metal gate stack. a portion of the protective structure is between the dielectric structure and the metal gate stack.
Inventor(s): Kuan-Ting PAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ruei JHAN of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/775, H01L29/66, H01L29/08, H01L21/8234
Abstract: a method for manufacturing a semiconductor structure is provided. the method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. the method includes forming a dummy gate structure across the fin structure. the method includes forming a gate spacer on the sidewall of the dummy gate structure. the method includes removing the dummy gate structure to expose the fin structure. the method includes partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers. the method includes forming dielectric spacers in the concave portions. the method includes removing the first semiconductor material layers to form gaps. the method includes forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.
Inventor(s): Yun Chen TENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Fong TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chi YU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng CHANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia YEO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/775, H01L29/66, H01L29/786, H01L21/8238
Abstract: a method includes forming fin structures upwardly extending above a semiconductor substrate; conformally depositing a first dielectric layer over the fin structures; depositing a flowable oxide over the first dielectric layer and between the fin structures; performing, at a temperature lower than about 500� c., a steam annealing process on the flowable oxide to cure the flowable oxide; after performing the steam annealing process, etching the cured flowable oxide until a top surface of the cured flowable oxide is lower than top surfaces of the fin structures; forming a second dielectric layer over the cured flowable oxide; forming a first gate structure extending across a first one of the fin structures and a second gate structure extending across a second one of the fin structures; forming first sources/drain regions on the first one of the fin structures and second sources/drain regions on the second one of the fin structures.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua PAN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao CHANG of Hsin-chu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/786, H01L29/775, H01L29/66, H01L29/417, H01L21/8234
Abstract: semiconductor structures and methods for forming the same are provided. the semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (s/d) structure formed adjacent to the gate structure. the semiconductor structure includes an s/d contact structure formed over the first s/d structure, and a dielectric wall formed below the gate structure and the s/d contact structure. the dielectric wall has a first portion directly below the s/d contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.
Inventor(s): Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ying LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L29/06, H01L29/423, H01L29/45, H01L29/786, H01L29/775, H01L21/285, H01L29/66
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. the semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.
Inventor(s): Chia-Hung Chu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin Liang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chien Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Harry CHIEN of Chandler AZ (US) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Min-Hsuan Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/45, H01L29/40, H01L29/66
Abstract: a semiconductor device includes parallel channel members, a gate structure, source/drain features, a silicide layer, and a source/drain contact. the parallel channel members are spaced apart from one another. the gate structure is wrapping around the channel members. the source/drain features are disposed besides the channel members and at opposite sides of the gate structure. the silicide layer is disposed on and in direct contact with the source/drain features. the source/drain contact is disposed on the silicide layer, wherein the source/drain contact includes a first source/drain contact and a second source/drain contact stacked on the first source/drain contact, and the second source/drain contact is separate from the silicide layer by the first source/drain contact.
Inventor(s): Meng-Pei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chi Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Tang Hung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cian-Yu Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/40
Abstract: a semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (s/d) regions, a backside contact, a first dielectric layer, and a conductive via. the at least one gate electrode is disposed in the substrate. the s/d regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. the backside contact is disposed above the s/d regions and the at least one gate electrode. the first dielectric layer is disposed between the backside contact and the plurality of s/d regions and the at least one gate electrode. the conductive via is extended through the first dielectric layer to electrically connect the s/d regions and the backside contact. the conductive via includes an anisotropic transport material or a topological material.
Inventor(s): Ching-Yu Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei Peng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L23/528, H01L23/48, H01L21/768
Abstract: a device includes a first row of active areas, a second row of active areas, and a first power via. the first row of active areas includes first active areas that extend in a first direction and second active areas that extend in the first direction. each of the first active areas has a first width in a second direction and each of the second active areas has a second width in the second direction that is smaller than the first width. the second row of active areas is situated above or below the first row of active areas and includes third active areas that extend in the first direction. each of the third active areas has the second width in the second direction. the first power via extends in a third direction between a transistor level of the device and a backside metal layer of the device and is situated between the first row of active areas and the second row of active areas.
Inventor(s): Ming Jian WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Xin Yong WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cun Cun CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia Liang ZHONG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/40, H01L27/088
Abstract: a method of biasing a substrate includes electrically connecting a silicide structure to a bias voltage supply. the method further includes conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures. the method further includes transferring the bias voltage from the silicide extension into a doped region of a substrate below the adjacent gate structures of the plurality of first gate structures.
Inventor(s): Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/45, H01L29/06, H01L29/08, H01L29/423, H01L29/417, H01L29/786, H01L29/775, H01L21/285, H01L29/66
Abstract: a semiconductor device and the manufacturing method thereof are described. the device includes semiconductor channel sheets, source and drain regions and a gate structure. the semiconductor channel sheets are arranged in parallel and spaced apart from one another. the source and drain regions are disposed beside the semiconductor channel sheets. the gate structure is disposed around and surrounding the semiconductor channel sheets. the silicide layer is disposed on the source region or the drain region. a contact structure is disposed on the silicide layer on the source region or the drain region. the contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact.
Inventor(s): Guan-Lin CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chien CHENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786, H01L21/02, H01L21/762
Abstract: a method of forming a semiconductor device includes etching trenches in a substrate to form semiconductor fins, filling a first one of the trenches with a dielectric fin, forming an insulation material in a second one of the trenches, performing a first recessing process to recess the insulation material and form a gap on a top of the dielectric fin, filling the gap with a dielectric cap, and forming a gate stack across the semiconductor fins and the dielectric fin.
Inventor(s): Kuo-Chang Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chuan Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Ting Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/1159, H01L29/51, H01L29/66
Abstract: provided are a ferroelectric memory device and a method of forming the same. the ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (s/d) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.
Inventor(s): Georgios Vellianitis of Heverlee (BE) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/1159, H01L29/786, H01L29/66
Abstract: a transistor includes a gate electrode, a ferroelectric layer, a source pattern, a drain pattern, and a channel layer. the ferroelectric layer is disposed on the gate electrode. the source pattern and the drain pattern are disposed over the ferroelectric layer. the channel layer has a base and fins protruding from the base. the base is in contact with the ferroelectric layer. the fins are located between the source pattern and the drain pattern.
Inventor(s): Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/51, H01L29/06, G11C11/22, H01L21/02, H01L29/66
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a switching layer over a semiconductor substrate. the switching layer comprises a first metal oxide. an upper conductive structure overlies the switching layer. the switching layer is spaced between opposing sidewalls of the upper conductive structure. a first dielectric layer is disposed along opposing sidewalls of the switching layer. the first dielectric layer comprises a second metal oxide different from the first metal oxide. a top surface of the switching layer and a top surface of the first dielectric layer directly underlie a bottom surface of the upper conductive structure.
Inventor(s): Kuo-Chiang TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Hsiang SU of Zhubei city (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Jing YU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hong HWANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Huei CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/66, H01L29/423, H01L29/417, H01L21/48, H01L21/768, H01L23/522
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a first insulating layer and first and second gate spacers in first and second openings of the first insulating layer, respectively, forming a first conductive gate stack adjacent to the first gate spacer and forming an insulating material adjacent to the second gate spacer after forming the first conductive gate stack. the method also includes covering the first conductive gate stack and the insulating material with a first insulating capping layer and a second insulating capping layer, respectively, and forming a source/drain contact structure between the first and second gate spacer layers. the top surface of the first insulating layer is higher than those of the insulating material and is substantially level with that of the first conductive gate stack.
Inventor(s): Yu-Lien HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jr-Hung LI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hao CHANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yu CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Yu CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/66, H01L29/40
Abstract: a method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ild) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a first recess between the gate spacers, forming a source/drain contact in the first ild layer, and forming a second interlayer dielectric (ild) layer to fill in the first recess between the gate spacers and over the source/drain contact.
Inventor(s): Yu-Chi LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ting WENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chiung Wen Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Cheng Chen of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/66, H01L29/06, H01L21/8234, H01L21/311
Abstract: a semiconductor device and a method of fabricating a semiconductor device are provided herein. the semiconductor device includes a substrate; a fin structure arranged on the substrate and including a ridge portion and a bottom portion between the ridge portion and the substrate, wherein the ridge portion comprises a channel region and a fin region between the channel region and the bottom portion, a critical dimension of the bottom portion in a cross-fin direction is gradually increased toward the substrate to twice or more of a critical dimension of the channel region in the cross-fin direction; a metal gate structure disposed on the fin structure extending the cross-fin direction; and an epitaxy region disposed beside the metal gate structure in a lengthwise direction of the fin structure and connected to the fin structure.
Inventor(s): Jiun-Ming Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chih Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Yuan Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chin Liu of Hualien County (TW) for taiwan semiconductor manufacturing company, ltd., Han-Yu Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., You-Ting Lin of Miaoli county (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Hong Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/3065, H01L29/66
Abstract: a method of manufacturing a semiconductor device includes at least the following steps. a protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. a recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.
Inventor(s): Chi-Lin Liu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chih Hsieh of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hsiang Ma of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K3/037, H03K19/21
Abstract: a circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. the control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. the control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. the control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.
Inventor(s): Huaixin XIAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Longbiao LEI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sinpei GOA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhang-Ying YAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K3/86, H03K3/037, H03K3/356
Abstract: a semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/11, G11C5/06, H01L23/528, H01L23/522
Abstract: a semiconductor device includes a first functional block and a second functional block. the first functional block includes a first substrate, a first device layer, a first interconnect structure and a plurality of first bonding patterns, and the first interconnect structure includes a plurality of first conductive patterns. the first bonding patterns are irregularly arranged. the second functional block is bonded to the first functional block. the second functional block includes a second substrate, a second device layer, a second interconnect structure and a plurality of second bonding patterns, and the second bonding patterns are in direct contact with the first bonding patterns.
Inventor(s): Gerben DOORNBOS of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd., Georgios Vellianitis of Heverlee (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/11587, H01L41/25
Abstract: a ferroelectric device and a wave computing device are provided. the ferroelectric device includes a first electrode, a second electrode, a ferroelectric layer and a wave guide. the ferroelectric layer is disposed between the first and second electrodes, and configured to transduce an electrical wave signal to a varying mechanical stress by piezoelectricity, or vice versa. a first polarization state or a second polarization state opposite to the first polarization state is programmed in the ferroelectric layer. the wave guide is in contact with the ferroelectric layer, and configured to transmit a wave signal resulted from or resulting the varying mechanical stress. the wave signal is in phase with the electrical wave signal when the ferroelectric layer is programmed with the first polarization state. the wave signal is out of phase with the electrical wave signal when the ferroelectric layer is programmed with the second polarization state.
Inventor(s): Kuen-Yi Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Chen of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Yi Ching Ong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/11507
Abstract: provided are ferroelectric tunnel junction (ftj) structures, memory devices, and methods for fabricating such structures and devices. an ftj structure includes a first electrode, a ferroelectric material layer, and a catalytic metal layer in contact with the ferroelectric material layer.
Inventor(s): Fu-Ting Sung of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hsueh Yang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Ming Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Chih Huang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wen Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chyuan Tzeng of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/10, H10N70/00
Abstract: device structures and methods for forming the same are provided. a device structure according to the present disclosure includes a first electrode and a second electrode disposed over an etch stop layer (esl), a first dielectric layer disposed between the first electrode and the second electrode, a phase-change material layer disposed over the first electrode, the first dielectric layer and the second electrode, an insulator layer disposed over the phase-change material layer, a metal feature disposed over the insulator layer, and a second dielectric layer disposed over the insulator layer, the first electrode, the second electrode, and the metal feature.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on February 15th, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- B08B3/02
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- Taiwan semiconductor manufacturing company, ltd.
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- H01L27/11507
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