Samsung electronics co., ltd. (20240136329). SEMICONDUCTOR PACKAGE simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Dae-Woo Kim of Seongnam-si (KR)
Eunseok Song of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240136329 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes two semiconductor chips with different widths, each having a wiring layer and through vias for power connection. The first chip receives power through its wiring structure and first through via, while the second chip receives power through its own wiring structure and second through via.
- First semiconductor chip with first wiring structure and through via for power connection
- Second semiconductor chip with second wiring structure and through via for power connection
- Different widths of the two semiconductor chips
- Power delivery through respective wiring structures and through vias
Potential Applications
This technology could be applied in various electronic devices requiring efficient power distribution between different semiconductor chips.
Problems Solved
This technology solves the problem of power delivery to semiconductor chips with different widths in a semiconductor package.
Benefits
The benefits of this technology include improved power distribution efficiency and optimized performance of electronic devices.
Potential Commercial Applications
A potential commercial application of this technology could be in the manufacturing of high-performance computing devices.
Possible Prior Art
One possible prior art could be a similar semiconductor package design with power delivery mechanisms for multiple semiconductor chips of different sizes.
Unanswered Questions
How does the technology impact the overall size of the semiconductor package?
The abstract does not provide information on whether this technology affects the overall size of the semiconductor package.
Are there any limitations to the power delivery efficiency of this technology?
The abstract does not mention any potential limitations to the power delivery efficiency of this technology.
Original Abstract Submitted
a semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.
