Samsung electronics co., ltd. (20240120280). SEMICONDUCTOR PACKAGE simplified abstract

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SEMICONDUCTOR PACKAGE

Organization Name

samsung electronics co., ltd.

Inventor(s)

Kyungdon Mun of Suwon-si (KR)

Shanghoon Seo of Suwon-si (KR)

Jihwang Kim of Suwon-si (KR)

Sangjin Baek of Suwon-si (KR)

Hyeonjeong Hwang of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240120280 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the patent application includes a complex structure involving multiple redistribution patterns, semiconductor devices, vertical connection conductors, heat dissipation elements, and molding layers. Here are the key points of the innovation:

  • First redistribution structure with a semiconductor device mounted on it
  • Molding layer surrounding the first semiconductor device
  • Second redistribution structure on top of the molding layer
  • Vertical connection conductors in the molding layer connecting the redistribution patterns
  • Second semiconductor device mounted on the second redistribution structure
  • Heat dissipation pad structure contacting the upper surface of the first semiconductor device
  • Heat dissipation plate spaced apart from the second semiconductor device along a horizontal direction

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      1. Potential Applications

The technology described in this patent application could be applied in various electronic devices requiring efficient heat dissipation and complex semiconductor packaging.

      1. Problems Solved

This technology solves the problem of heat dissipation in densely packed semiconductor devices while providing a reliable vertical connection between different redistribution patterns.

      1. Benefits

The benefits of this technology include improved thermal management, increased reliability of vertical connections, and enhanced performance of semiconductor devices.

      1. Potential Commercial Applications

This technology could find commercial applications in high-performance computing, telecommunications equipment, automotive electronics, and other industries requiring advanced semiconductor packaging solutions.

      1. Possible Prior Art

One possible prior art for this technology could be the use of heat dissipation structures in semiconductor packages to improve thermal performance and reliability.

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        1. Unanswered Questions
      1. How does this technology compare to existing heat dissipation solutions in semiconductor packaging?

The article does not provide a direct comparison with existing heat dissipation solutions in semiconductor packaging. It would be interesting to know the specific advantages of this technology over traditional methods.

      1. What are the specific challenges in manufacturing semiconductor packages with such complex structures?

The article does not delve into the manufacturing process or potential challenges faced in producing semiconductor packages with multiple redistribution patterns and vertical connection conductors. Understanding these challenges could provide insights into the feasibility and scalability of this technology.


Original Abstract Submitted

a semiconductor package includes a first redistribution structure, a first semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first semiconductor device, a second redistribution structure disposed on the molding layer and the first semiconductor device, a plurality of vertical connection conductors vertically extending in the molding layer and electrically connecting the first redistribution pattern to the second redistribution pattern, a second semiconductor device mounted on the second redistribution structure, the second semiconductor device and the first semiconductor device vertically and partially overlapping each other, a heat dissipation pad structure contacting an upper surface of the first semiconductor device, and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device along a first straight line extending in a horizontal direction that is parallel to the upper surface of the first semiconductor device.