NANYA TECHNOLOGY CORPORATION patent applications on February 8th, 2024
Patent Applications by NANYA TECHNOLOGY CORPORATION on February 8th, 2024
NANYA TECHNOLOGY CORPORATION: 36 patent applications
NANYA TECHNOLOGY CORPORATION has applied for patents in the areas of H01L21/768 (12), H01L23/528 (12), H01L23/532 (11), H01L23/00 (9), H01L23/53238 (7)
With keywords such as: semiconductor, structure, layer, substrate, device, conductive, pad, disposed, bonding, and positioned in patent application abstracts.
Patent Applications by NANYA TECHNOLOGY CORPORATION
20240044956.ELECTRONIC DEVICE AND PHASE DETECTOR_simplified_abstract_(nanya technology corporation)
Inventor(s): WU-DER YANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): G01R25/00, H03K17/687
Abstract: an electronic device and phase detector are provided. the phase detector includes a first input terminal, a second input terminal, a first input buffer, and a second input buffer. the first input buffer is electrically connected to the first input terminal. the second input buffer is electrically connected to the second input terminal.
20240044957.ELECTRONIC DEVICE AND PHASE DETECTOR_simplified_abstract_(nanya technology corporation)
Inventor(s): WU-DER YANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): G01R25/00, H03K17/687
Abstract: an electronic device and phase detector are provided. the phase detector includes a first input terminal, a second input terminal, a first input buffer, and a second input buffer. the first input buffer is electrically connected to the first input terminal. the second input buffer is electrically connected to the second input terminal.
20240044976.ELECTRONIC DEVICE AND PHASE DETECTOR_simplified_abstract_(nanya technology corporation)
Inventor(s): WU-DER YANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): G01R31/317, H03K17/687
Abstract: an electronic device including a phase detector is provided. the phase detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first equalizer device. the first transistor has a first input terminal configured to receive a first signal. the second transistor has a second input terminal configured to receive a second signal. the third transistor is electrically connected to the first transistor and has a first output terminal. the fourth transistor is electrically connected to the second transistor and has a second output terminal. the first equalizer device is connected between the first output terminal and the second input terminal.
20240044977.ELECTRONIC DEVICE AND PHASE DETECTOR_simplified_abstract_(nanya technology corporation)
Inventor(s): WU-DER YANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): G01R31/317, H03K17/687
Abstract: an electronic device including a phase detector is provided. the phase detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first equalizer device. the first transistor has a first input terminal configured to receive a first signal. the second transistor has a second input terminal configured to receive a second signal. the third transistor is electrically connected to the first transistor and has a first output terminal. the fourth transistor is electrically connected to the second transistor and has a second output terminal. the first equalizer device is connected between the first output terminal and the second input terminal.
Inventor(s): HUAN-YUNG YEH of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/308, H01L21/033, H01L21/311, H01L21/3213
Abstract: the present application discloses a semiconductor device including a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate. the semiconductor device further includes a transistor and a resistor. the transistor is disposed between the first isolation structure and the second isolation structure, and includes a gate electrode and a first source/drain (s/d) region. the resistor is disposed between the second isolation structure and the third isolation structure, and includes a resistor electrode. the first s/d region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode.
Inventor(s): Zhi-Xuan SHEN of Taipei City (TW) for nanya technology corporation
IPC Code(s): H01L21/311, H01L21/02
Abstract: a method of manufacturing a semiconductor includes: providing a stacked structure comprising a first oxide layer, a second oxide layer, and a metal layer stacked between the first oxide layer and the second oxide layer; patterning the second oxide layer; forming a mask layer on the patterned second oxide layer; introducing a gas mixture to the stacked structure; and performing a pulsing plasma process to the stacked structure through the mask layer to form at least one via running through the first oxide layer, the metal layer, and the second oxide layer.
Inventor(s): MENG-LIANG WEI of TAOYUAN CITY (TW) for nanya technology corporation, SUN-FU CHOU of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L21/673, H01L21/02
Abstract: a gas purge device includes a first nozzle and a gas gate. the first nozzle is coupled to a front-opening unified pod (foup) through a first port of the foup. the gas gate is coupled to the first nozzle via a first pipe. the gas gate includes a first mass flow controller (mfc), a second mfc, and a first switch unit. the first mfc is configured to control a first flow of a first gas. the second mfc is configured to control a second flow of a second gas. the first switch unit is coupled to the first mfc and the second mfc, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.
Inventor(s): Chuan-Lin HSIAO of Taoyuan City (TW) for nanya technology corporation, Wei-Ming LIAO of Taoyuan City (TW) for nanya technology corporation
IPC Code(s): H01L21/762, H01L29/06
Abstract: a manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/18, H01L23/522, H01L21/768
Abstract: the present application discloses a semiconductor device and a method for fabricating the semiconductor device. the semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. the cushion structure includes a porous polymeric material.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/18, H01L23/522, H01L21/768
Abstract: the present application discloses a semiconductor device and a method for fabricating the semiconductor device. the semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. the cushion structure includes a porous polymeric material.
Inventor(s): LIANG-PIN CHOU of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/48, H01L23/522, H01L21/768, H01L23/532
Abstract: the present disclosure provides a semiconductor device. the semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. the intervening bonding layer is positioned on the die stack. the carrier structure is disposed on the intervening bonding layer opposite to the die stack. the carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. the heat dissipation unit includes composite vias and conductive plates. each of the composite vias includes a first through semiconductor via and a second through semiconductor via. the conductive plates are couple to the composite vias.
Inventor(s): WU-DER YANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/31, H01L23/13, H01L21/48
Abstract: a wbga package and a method of manufacturing a wbga package are provided. the wbga package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. the wbga package also includes an electronic component having an active surface over the second through hole of the second substrate.
Inventor(s): WU-DER YANG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/498, H01L23/00, H01L21/48, H01L23/31, H01L23/13
Abstract: a wbga package and a method of manufacturing a wbga package are provided. the wbga package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. the wbga package also includes an electronic component having an active surface over the second through hole of the second substrate.
Inventor(s): Yi-Jen LO of New Taipei City (TW) for nanya technology corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/48, H01L23/532
Abstract: the present disclosure provides a method of manufacturing a semiconductor device. the method includes: forming a first via and a second via on a semiconductor structure, wherein the semiconductor structure includes a first dielectric layer, a first barrier layer, a first metal, a second barrier layer, a second dielectric layer, a substrate, and a second metal; forming a third dielectric layer on the substrate and a bottom and the inner sidewalls of the first via and the second via; punching through the third dielectric layer on the bottom of the first via and the second via; forming a third barrier layer on the substrate and in the first via and the second via; removing oxides formed from the first metal and the second metal; forming a fourth barrier layer; and forming a conductive material in the first via and the second via.
Inventor(s): MIN-CHUNG CHENG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L23/532, H01L21/768
Abstract: the present application provides a semiconductor device and a method of manufacturing the semiconductor device. the semiconductor device includes a substrate and a wiring structure. the wiring structure includes at least one metal interconnect disposed on the substrate, at least one conductive feature disposed on the metal interconnect, and at least one diffusing barrier liner surrounding the conductive feature. the conductive feature has a head portion and a neck portion sandwiched between the metal interconnect and the head portion. the neck portion can have a first critical dimension, which gradually decreases at positions of increasing distance from the head portion.
Inventor(s): MIN-CHUNG CHENG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/532
Abstract: the present application provides a semiconductor device and a method of manufacturing the semiconductor device. the semiconductor device includes a substrate and a wiring structure. the wiring structure includes at least one metal interconnect disposed on the substrate, at least one conductive feature disposed on the metal interconnect, and at least one diffusing barrier liner surrounding the conductive feature. the conductive feature has a head portion and a neck portion sandwiched between the metal interconnect and the head portion. the neck portion can have a first critical dimension, which gradually decreases at positions of increasing distance from the head portion.
Inventor(s): MIN-CHUNG CHENG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L23/522, H01L21/768
Abstract: the present application provides a wiring structure, a semiconductor device having the wiring structure, and a method of manufacturing the semiconductor device. the wiring structure includes a substrate, a metallic layer above the substrate, at least one first conductive feature and at least one second conductive feature. the first and second conductive features are disposed between the substrate and the metallic layer; the first conductive feature has a first critical dimension, and the second conductive feature has a second critical dimension less than the first critical dimension. an effective resistance of the wiring structure can be adjusted by changing the critical dimensions of the first and second conductive features. the semiconductor device including the wiring structure and a method of manufacturing the semiconductor device are also provided.
Inventor(s): MIN-CHUNG CHENG of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
Abstract: the present application provides a wiring structure, a semiconductor device having the wiring structure, and a method of manufacturing the semiconductor device. the wiring structure includes a substrate, a metallic layer above the substrate, at least one first conductive feature and at least one second conductive feature. the first and second conductive features are disposed between the substrate and the metallic layer; the first conductive feature has a first critical dimension, and the second conductive feature has a second critical dimension less than the first critical dimension. an effective resistance of the wiring structure can be adjusted by changing the critical dimensions of the first and second conductive features. the semiconductor device including the wiring structure and a method of manufacturing the semiconductor device are also provided.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/532, H01L23/528, H01L21/311, H01L21/3115, H01L21/3205
Abstract: a semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. the first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. the semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. the first lower semiconductor structure and the first upper semiconductor structure include different materials. the semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. the first oxide portion has an l-shape.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/532, H01L21/311, H01L21/3115, H01L23/528, H01L21/3205
Abstract: a semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. the first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. the semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. the first lower semiconductor structure and the first upper semiconductor structure include different materials. the semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. the first oxide portion has an l-shape.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/532, H01L23/528, H01L21/768
Abstract: a semiconductor device and method for manufacturing the same are provided. the semiconductor device includes a substrate, an interconnection structure, a first isolation feature, and a second isolation feature. the interconnection structure has a first lateral surface and a second lateral surface. the first isolation feature is disposed on the first lateral surface of the interconnection structure. the second isolation feature is disposed on the second lateral surface of the interconnection structure. the first isolation feature is different from the second isolation feature.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/532, H01L23/528, H01L21/768
Abstract: a semiconductor device and method for manufacturing the same are provided. the semiconductor device includes a substrate, an interconnection structure, a first isolation feature, and a second isolation feature. the interconnection structure has a first lateral surface and a second lateral surface. the first isolation feature is disposed on the first lateral surface of the interconnection structure. the second isolation feature is disposed on the second lateral surface of the interconnection structure. the first isolation feature is different from the second isolation feature.
Inventor(s): CHIH-HSUAN YEH of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/544, G03F7/20
Abstract: a semiconductor device and method for manufacturing the same are provided. the semiconductor device includes a substrate, a first pattern and a second pattern. the first pattern is disposed on the substrate. the first pattern includes a first segment and a second segment, each of which extends along a first direction. the second pattern is disposed on the first pattern. the second pattern includes a first part extending along a second direction different from the first direction. the first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. the first pattern and the second pattern are associated with an overlay error.
Inventor(s): CHIH-HSUAN YEH of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/544, G03F7/20
Abstract: a semiconductor device and method for manufacturing the same are provided. the semiconductor device includes a substrate, a first pattern and a second pattern. the first pattern is disposed on the substrate. the first pattern includes a first segment and a second segment, each of which extends along a first direction. the second pattern is disposed on the first pattern. the second pattern includes a first part extending along a second direction different from the first direction. the first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. the first pattern and the second pattern are associated with an overlay error.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/00, H01L21/48, H01L23/488, H01L23/532
Abstract: a semiconductor device includes a semiconductor substrate having a bonding pad, and a first dielectric layer disposed over the semiconductor substrate. a portion of the bonding pad is exposed by the first dielectric layer. the semiconductor device also includes a metal oxide layer disposed over the portion of the bonding pad, and a wire bond penetrating through the metal oxide layer to bond to the bonding pad. the portion of the bonding pad is entirely covered by the metal oxide layer and the wire bond.
Inventor(s): SHING-YIH SHIH of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/00
Abstract: a semiconductor package structure includes a first semiconductor wafer including a first bonding pad. the semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. the second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. the semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. a portion of the first via is disposed between the second bonding pad and the third bonding pad.
20240047395.SEMICONDUCTOR STRUCTURE_simplified_abstract_(nanya technology corporation)
Inventor(s): Sheng-Fu HUANG of New Taipei City (TW) for nanya technology corporation, Shing-Yih SHIH of New Taipei City (TW) for nanya technology corporation
IPC Code(s): H01L23/00, H01L25/065
Abstract: a semiconductor structure includes a first chip and a second chip bonded to the first chip. the first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (rdl) over a conductive line of the first multi-level interconnect structure, a compact layer over the first rdl and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first rdl. the second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.
Inventor(s): CHUN-CHENG LIAO of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L23/00, H01L23/31
Abstract: a semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern, wherein the interconnect structure includes a graphene liner. the semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. the inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. the semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. the semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L25/18, H01L23/00, H01L23/532, H01L21/768, H01L25/00
Abstract: the present application discloses a semiconductor device and a method for fabricating the semiconductor device. the semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L25/18, H01L23/00, H01L23/532, H01L21/768, H01L25/00
Abstract: the present application discloses a semiconductor device and a method for fabricating the semiconductor device. the semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.
Inventor(s): Shih-Ting HUANG of New Taipei City (TW) for nanya technology corporation
IPC Code(s): H10B12/00
Abstract: a method of forming a semiconductor structure includes following steps. a substrate is provided. the substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. a dielectric stack is formed on the substrate. a poly layer is formed on the dielectric stack. the poly layer and the dielectric stack are etched to form an opening to expose the contact of the substrate. a conductive film is formed in the opening and an ald oxide layer is deposited on a sidewall of the opening. in addition, a semiconductor structure is also disclosed herein.
Inventor(s): YUAN-YUAN LIN of TAOYUAN CITY (TW) for nanya technology corporation
IPC Code(s): H01L29/06, H10B12/00
Abstract: the present disclosure provides a semiconductor device includes a semiconductor substrate, a first metal plug, a second metal plug, a third metal plug, a fourth metal plug, and a boron nitride layer. the first metal plug and the second metal plug are disposed over a pattern-dense region of the semiconductor substrate. the third metal plug and the fourth metal plug are disposed over a pattern-loose region of the semiconductor substrate. the boron nitride layer is disposed over the semiconductor substrate. each of the first metal plug and the second metal plug includes a barrier layer and a conductive feature. the barrier layer is contact with the semiconductor substrate. the conductive feature is disposed over the barrier layer. the conductive feature is separated from the semiconductor substrate by the barrier layer.
Inventor(s): Chia Che CHIANG of New Taipei City (TW) for nanya technology corporation, Jen-I LAI of Taoyuan City (TW) for nanya technology corporation, Chun-Heng WU of Taoyuan City (TW) for nanya technology corporation
IPC Code(s): H01L27/108
Abstract: a method of forming semiconductor structure includes forming a dielectric stack over a substrate. a mask layer is formed over the dielectric stack. a first opening is formed in the mask layer to expose dielectric stack. a second opening is formed in the dielectric stack to expose the substrate, wherein the second opening is communicated with the first opening. a fill layer is formed in the first opening and the second opening. the mask layer and the fill layer are removed such that sidewalls of the dielectric stack are exposed. a capacitor is formed in the second opening of the dielectric stack.
Inventor(s): TSU-CHIEH AI of TAITUNG CITY (TW) for nanya technology corporation
IPC Code(s): H10B12/00, H01L23/00, H01L29/417
Abstract: a semiconductor device and a method of manufacturing a semiconductor device are provided. the semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. the first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. the semiconductor device also includes a capacitor structure at least partially disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.
Inventor(s): YU-TING LIN of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H01L27/108
Abstract: a method of manufacturing a semiconductor structure and a semiconductor structure are provided. the method includes: providing a sacrificial structure disposed on a substrate; arranging a photomask to cover the sacrificial structure, wherein the photomask includes a plurality of transparent portions, a plurality of central opaque portions, at least one first edge opaque portion and at least one second edge opaque portion between the first edge opaque portion and the central opaque portions; removing portions of the sacrificial structure to form a plurality of central openings, at least one first edge opening and at least one second edge opening through the central opaque portions, the first edge opaque portion, the second edge opaque portion and the transparent portions; and forming at least one edge word line on the substrate through the second edge opening and forming a plurality of central word lines on the substrate through the central openings.
Inventor(s): YU-TING LIN of NEW TAIPEI CITY (TW) for nanya technology corporation
IPC Code(s): H10B12/00
Abstract: a method of manufacturing a semiconductor structure and a semiconductor structure are provided. the method includes: providing a sacrificial structure disposed on a substrate; arranging a photomask to cover the sacrificial structure, wherein the photomask includes a plurality of transparent portions, a plurality of central opaque portions, at least one first edge opaque portion and at least one second edge opaque portion between the first edge opaque portion and the central opaque portions; removing portions of the sacrificial structure to form a plurality of central openings, at least one first edge opening and at least one second edge opening through the central opaque portions, the first edge opaque portion, the second edge opaque portion and the transparent portions; and forming at least one edge word line on the substrate through the second edge opening and forming a plurality of central word lines on the substrate through the central openings.
NANYA TECHNOLOGY CORPORATION patent applications on February 8th, 2024
- NANYA TECHNOLOGY CORPORATION
- G01R25/00
- H03K17/687
- Nanya technology corporation
- G01R31/317
- H01L21/308
- H01L21/033
- H01L21/311
- H01L21/3213
- H01L21/02
- H01L21/673
- H01L21/762
- H01L29/06
- H01L23/18
- H01L23/522
- H01L21/768
- H01L23/48
- H01L23/532
- H01L23/498
- H01L23/00
- H01L23/31
- H01L23/13
- H01L21/48
- H01L23/528
- H01L21/3115
- H01L21/3205
- H01L23/544
- G03F7/20
- H01L23/488
- H01L25/065
- H01L25/18
- H01L25/00
- H10B12/00
- H01L27/108
- H01L29/417
- H01L23/53238
