Intel corporation (20240128162). NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION simplified abstract
Contents
- 1 NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
Organization Name
Inventor(s)
Ravindranath Mahajan of Chandler AZ (US)
Debendra Mallik of Chandler AZ (US)
Sujit Sharan of Chandler AZ (US)
Digvijay Raorane of Chandler AZ (US)
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240128162 titled 'NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
Simplified Explanation
The abstract of the patent application describes electronic packages and methods of forming them, including a base substrate with through substrate vias, a die, a cavity within the base substrate, and a component within the cavity.
- The electronic package includes a base substrate with through substrate vias.
- A die is positioned over the base substrate.
- A cavity is formed within the base substrate, at least partially within the footprint of the die.
- A component is placed within the cavity.
Potential Applications
This technology could be applied in the manufacturing of electronic devices, such as smartphones, tablets, and computers.
Problems Solved
This technology solves the problem of efficiently integrating components within electronic packages, improving overall performance and reliability.
Benefits
The benefits of this technology include enhanced functionality, increased compactness, and improved thermal management within electronic devices.
Potential Commercial Applications
The potential commercial applications of this technology include consumer electronics, automotive electronics, and industrial equipment.
Possible Prior Art
One possible prior art for this technology could be the use of cavity structures in electronic packages to improve thermal performance and component integration.
Unanswered Questions
How does this technology impact the overall cost of electronic package manufacturing?
The abstract does not provide information on the cost implications of implementing this technology in electronic package manufacturing.
What specific materials are used in the base substrate and components of the electronic package?
The abstract does not detail the specific materials used in the construction of the base substrate and components of the electronic package.
Original Abstract Submitted
embodiments disclosed herein include electronic packages and methods of forming such electronic packages. in an embodiment, the electronic package comprises a base substrate. the base substrate may have a plurality of through substrate vias. in an embodiment, a first die is over the base substrate. in an embodiment a first cavity is disposed into the base substrate. in an embodiment, the first cavity is at least partially within a footprint of the first die. in an embodiment, a first component is in the first cavity.
