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| − | '''Summary of the patent applications from Applied Materials, Inc. on November 9th, 2023'''
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| − |
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| − | Applied Materials, Inc. has recently filed several patents related to semiconductor processing and equipment. These patents cover various aspects of the semiconductor manufacturing process, including impedance tuning, defect correction, film deposition, etching, and substrate handling.
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| − |
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| − | In terms of impedance tuning, one patent application describes a method for measuring voltage and current signals of a transmission line in a semiconductor processing tool. These analog signals are then converted into digital signals, and a u-vector is calculated from them. The real components of the u-vector are used to determine the position of a first capacitor, while the imaginary components are used to determine the position of a second capacitor.
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| − |
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| − | Another patent application focuses on correcting defects in microLED structures caused by a mesa etch process. The method involves a dry etch process that incrementally removes a small outer layer of the structures, preserving their overall shape. The resulting smooth surface is suitable for the application of a dielectric layer. The dry etch process consists of two steps: the first gas reacts with the surface to form a gallium compound layer, and the second gas selectively removes that layer. This process can be plasma-based or reactive thermal etches.
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| − |
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| − | Applied Materials, Inc. has also filed patents related to film deposition and etching. One patent application describes methods for depositing transition metal dichalcogenide films on a substrate, as well as converting transition metal oxide films to transition metal dichalcogenide films. The process involves exposing the substrate to metal and chalcogenide precursors to form the desired films.
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| − |
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| − | In terms of etching, one patent application describes a method for etching metal-containing features using a pattern mask. The exposed portion of the feature is then etched and replaced with a filler dielectric, reducing unwanted conductivity between adjacent features.
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| − |
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| − | Applied Materials, Inc. has also developed innovative equipment for semiconductor processing. One patent application describes a process chamber with coaxial lift devices, including a bottom bowl lift and a pedestal lift. These lifts can independently move and tilt to create a small and symmetric process volume, improving film uniformity on processed substrates.
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| − |
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| − | In summary, Applied Materials, Inc. has recently filed patents covering various aspects of semiconductor processing, including impedance tuning, defect correction, film deposition, etching, and equipment design. These patents demonstrate the company's commitment to advancing semiconductor manufacturing processes and improving the efficiency and quality of semiconductor devices.
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| − |
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| − | Notable applications:
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| − |
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| − | * Impedance tuning in semiconductor processing tools.
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| − | * Defect correction in microLED structures.
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| − | * Deposition of transition metal dichalcogenide films.
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| − | * Etching of metal-containing features.
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| − | * Coaxial lift devices for process chambers.
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| − | * Semiconductor processing using carbon-containing precursors.
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| − | * Plasma etch pulse for sample etching.
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| − | * Semiconductor processing using silicon and carbon precursors.
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| | ==Patent applications for Applied Materials, Inc. on November 9th, 2023== | | ==Patent applications for Applied Materials, Inc. on November 9th, 2023== |
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| | Fei Wang | | Fei Wang |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application is about coated drug compositions and how to prepare them using a low temperature o-zone based silicon oxide coating.
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| − | - The method involves coating active pharmaceutical ingredient particles using a silicon precursor and ozone.
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| − | - The coating process is done at a low temperature.
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| − | - The purpose of the coating is to enhance the drug's effectiveness or stability.
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| − | - The patent application provides a specific method for achieving this coating.
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| − |
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| − | '''Abstract'''
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| − | This disclosure pertains to coated drug compositions and methods of preparing coated drug compositions with a low temperature o-zone based silicon oxide coating. Specifically, the instant application discloses a method to coat active pharmaceutical ingredient particles using a silicon precursor and ozone at a low temperature.
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| | | | |
| | ===CHEMICAL MECHANICAL POLISHING TEMPERATURE SCANNING APPARATUS FOR TEMPERATURE CONTROL ([[US Patent Application 18356604. CHEMICAL MECHANICAL POLISHING TEMPERATURE SCANNING APPARATUS FOR TEMPERATURE CONTROL simplified abstract|18356604]])=== | | ===CHEMICAL MECHANICAL POLISHING TEMPERATURE SCANNING APPARATUS FOR TEMPERATURE CONTROL ([[US Patent Application 18356604. CHEMICAL MECHANICAL POLISHING TEMPERATURE SCANNING APPARATUS FOR TEMPERATURE CONTROL simplified abstract|18356604]])=== |
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| | Hari Soundararajan | | Hari Soundararajan |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a chemical mechanical polishing apparatus that is used for polishing substrates.
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| − | * The apparatus includes a platen with a top surface that holds a polishing pad.
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| − | * A carrier head is used to hold the substrate against the polishing surface of the pad during the polishing process.
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| − | * The apparatus also includes a temperature monitoring system.
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| − | * The temperature monitoring system uses a non-contact thermal sensor positioned above the platen.
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| − | * The sensor has a field of view that covers a portion of the polishing pad.
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| − | * The sensor can be rotated by a motor to move the field of view across the polishing pad.
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| − | * The purpose of the temperature monitoring system is to measure the temperature of the polishing pad during the polishing process.
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| − |
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| − | '''Abstract'''
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| − | A chemical mechanical polishing apparatus includes a platen having a top surface to hold a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad during a polishing process, and a temperature monitoring system. The temperature monitoring system includes a non-contact thermal sensor positioned above the platen that has a field of view of a portion of the polishing pad on the platen. The sensor is rotatable by the motor around an axis of rotation so as to move the field of view across the polishing pad.
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| | | | |
| | ===Carrier Head Membrane With Regions of Different Roughness ([[US Patent Application 18351260. Carrier Head Membrane With Regions of Different Roughness simplified abstract|18351260]])=== | | ===Carrier Head Membrane With Regions of Different Roughness ([[US Patent Application 18351260. Carrier Head Membrane With Regions of Different Roughness simplified abstract|18351260]])=== |
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| | Young J. Paik | | Young J. Paik |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes an apparatus used in substrate chemical mechanical polishing.
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| − | * The apparatus includes a flexible membrane that is used with a carrier head.
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| − | * The membrane has an outer surface that acts as a substrate receiving surface.
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| − | * The outer surface is divided into a central portion and an edge portion.
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| − | * The central portion has a higher surface roughness compared to the edge portion.
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| − | * The purpose of this design is to provide different levels of surface roughness for different areas of the substrate.
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| − | * This can help improve the polishing process by optimizing the contact between the substrate and the membrane.
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| − | * The innovation lies in the specific design of the membrane with varying surface roughness.
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| − |
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| − | '''Abstract'''
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| − | An apparatus comprises a flexible membrane for use with a carrier head of a substrate chemical mechanical polishing apparatus. The membrane comprises an outer surface providing a substrate receiving surface, wherein the outer surface has a central portion and an edge portion surrounding the central portion, wherein the central portion has a first surface roughness and the edge portion has a second surface roughness, the first surface roughness being greater than the second surface roughness.
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| | | | |
| | ===COMPLIANT INNER RING FOR A CHEMICAL MECHANICAL POLISHING SYSTEM ([[US Patent Application 17735655. COMPLIANT INNER RING FOR A CHEMICAL MECHANICAL POLISHING SYSTEM simplified abstract|17735655]])=== | | ===COMPLIANT INNER RING FOR A CHEMICAL MECHANICAL POLISHING SYSTEM ([[US Patent Application 17735655. COMPLIANT INNER RING FOR A CHEMICAL MECHANICAL POLISHING SYSTEM simplified abstract|17735655]])=== |
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| | Jeonghoon Oh | | Jeonghoon Oh |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application describes carrier heads for a chemical mechanical polishing apparatus.
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| − | - The carrier heads have a carrier body and a substrate mounting surface.
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| − | - The carrier heads have an inner ring that surrounds the edge of a substrate.
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| − | - The inner ring can be moved radially.
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| − | - The carrier heads also have an outer ring that is in contact with the inner ring.
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| − |
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| − | '''Abstract'''
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| − | Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first end having a first surface that faces the carrier body and a second end having a second surface opposite the first surface. The second end of the inner ring may be radially displaceable. The carrier heads may include an outer ring having an inner surface that is disposed against an outer surface of the inner ring.
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| | | | |
| | ===POLISHING HEAD WITH LOCAL INNER RING DOWNFORCE CONTROL ([[US Patent Application 17735674. POLISHING HEAD WITH LOCAL INNER RING DOWNFORCE CONTROL simplified abstract|17735674]])=== | | ===POLISHING HEAD WITH LOCAL INNER RING DOWNFORCE CONTROL ([[US Patent Application 17735674. POLISHING HEAD WITH LOCAL INNER RING DOWNFORCE CONTROL simplified abstract|17735674]])=== |
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| | Jeonghoon Oh | | Jeonghoon Oh |
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| − |
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| − | '''Brief explanation'''
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| − | - The abstract describes a patent application for carrier heads used in a chemical mechanical polishing apparatus.
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| − | - The carrier heads have a carrier body and a substrate mounting surface.
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| − | - They also have an inner ring that surrounds the edge of a substrate placed on the mounting surface.
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| − | - The inner ring has a first surface facing the carrier body and a second surface on the opposite side.
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| − | - The carrier heads have at least one downforce control actuator positioned above the first surface of the inner ring.
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| − | - The actuator is located at a specific position around the inner ring's circumference.
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| − | - The purpose of the invention is to provide improved control over the downforce applied to the substrate during the polishing process.
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| − |
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| − | '''Abstract'''
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| − | Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first surface that faces the carrier body and a second surface opposite the first surface. The carrier heads may include at least one downforce control actuator disposed above the first surface of the inner ring at a discrete position about a circumference of the inner ring.
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| | | | |
| | ===METHODS, SYSTEMS, AND APPARATUS FOR INKJET PRINTING SELF-ASSEMBLED MONOLOAYER (SAM) STRUCTURES ON SUBSTRATES ([[US Patent Application 18142305. METHODS, SYSTEMS, AND APPARATUS FOR INKJET PRINTING SELF-ASSEMBLED MONOLOAYER (SAM) STRUCTURES ON SUBSTRATES simplified abstract|18142305]])=== | | ===METHODS, SYSTEMS, AND APPARATUS FOR INKJET PRINTING SELF-ASSEMBLED MONOLOAYER (SAM) STRUCTURES ON SUBSTRATES ([[US Patent Application 18142305. METHODS, SYSTEMS, AND APPARATUS FOR INKJET PRINTING SELF-ASSEMBLED MONOLOAYER (SAM) STRUCTURES ON SUBSTRATES simplified abstract|18142305]])=== |
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| | Yingdong LUO | | Yingdong LUO |
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| − |
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| − | '''Brief explanation'''
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| − | - The present disclosure is about a method, system, and apparatus for inkjet printing self-assembled monolayer (SAM) structures on substrates.
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| − | - The method involves printing one or more SAM layers on a substrate surface in a localized manner, leaving a portion of the substrate surface exposed to the inkjet chamber's processing region.
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| − | - The printing process includes spraying subsections of the substrate surface with an ink that has a SAM composition.
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| − | - The SAM composition of the ink includes an active component and a hydrophobic tail.
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| − | - This innovation allows for precise and controlled deposition of SAM structures on substrates using inkjet printing technology.
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| − |
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| − | '''Abstract'''
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| − | Embodiments of the present disclosure relate to methods, systems, and apparatus for inkjet printing self-assembled monolayer (SAM) structures on substrates. In one embodiment, which can be combined with other embodiments, one or more SAM layers are printed on a substrate surface of a substrate in a localized manner such that a portion of the substrate surface is left exposed to a processing region of the inkjet chamber. The printing includes spraying one or more subsections of the substrate surface with an ink, the ink having a SAM composition. The SAM composition includes an active component, and a hydrophobic tail.
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| | | | |
| | ===ALD CYCLE TIME REDUCTION USING PROCESS CHAMBER LID WITH TUNABLE PUMPING ([[US Patent Application 18224206. ALD CYCLE TIME REDUCTION USING PROCESS CHAMBER LID WITH TUNABLE PUMPING simplified abstract|18224206]])=== | | ===ALD CYCLE TIME REDUCTION USING PROCESS CHAMBER LID WITH TUNABLE PUMPING ([[US Patent Application 18224206. ALD CYCLE TIME REDUCTION USING PROCESS CHAMBER LID WITH TUNABLE PUMPING simplified abstract|18224206]])=== |
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| | Muhannad Mustafa | | Muhannad Mustafa |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application describes process chamber lids that have a pumping liner with a showerhead and gas funnel within an open central region.
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| − | - The showerhead and gas funnel are spaced apart to create a gap, and the gas funnel has an opening to allow gas to flow into the gap.
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| − | - The gas funnel has multiple apertures that extend from the front surface to a common region near the back surface.
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| − | - A purge ring is in contact with the back surface of the gas funnel and has a circular channel on its bottom surface that aligns with the common area of the apertures.
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| − | - The purpose of this design is to provide an improved gas flow distribution within the process chamber.
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| − | - The gap between the showerhead and gas funnel allows for better mixing of the gas, leading to more uniform processing.
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| − | - The apertures in the gas funnel and the circular channel in the purge ring help to evenly distribute the gas flow across the process chamber.
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| − | - This innovation aims to enhance the efficiency and effectiveness of processes carried out in the process chamber.
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| − |
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| − | '''Abstract'''
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| − | Process chamber lids having a pumping liner with a showerhead and gas funnel within an open central region are described. The showerhead is spaced a distance from the gas funnel to form a gap and the gas funnel has an opening to provide a flow of gas into the gap. The gas funnel includes a plurality of apertures extending from the front surface to a common region adjacent the back surface of the gas funnel. A purge ring is in contact with the back surface of the gas funnel and aligned so that a circular channel formed in the bottom surface of the purge ring body is positioned adjacent the common area of the apertures in the gas funnel.
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| | | | |
| | ===APPARATUS AND METHODS TO PROMOTE WAFER EDGE TEMPERATURE UNIFORMITY ([[US Patent Application 17862138. APPARATUS AND METHODS TO PROMOTE WAFER EDGE TEMPERATURE UNIFORMITY simplified abstract|17862138]])=== | | ===APPARATUS AND METHODS TO PROMOTE WAFER EDGE TEMPERATURE UNIFORMITY ([[US Patent Application 17862138. APPARATUS AND METHODS TO PROMOTE WAFER EDGE TEMPERATURE UNIFORMITY simplified abstract|17862138]])=== |
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| | Zubin HUANG | | Zubin HUANG |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a shadow ring for a processing chamber, such as a semiconductor processing chamber, that includes a feature to reduce heat transfer between its lip and the rest of the body.
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| − |
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| − | * The shadow ring is an annular member with a lip that projects inwardly.
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| − | * It is used in processing chambers, particularly in semiconductor processing.
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| − | * The innovation includes a feature that mitigates heat transfer between the lip and the rest of the body.
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| − | * This feature consists of a series of apertures that extend from the upper surface to the lower surface of the shadow ring.
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| − | * The apertures are connected by necks, creating bottlenecks that hinder conductive heat transfer.
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| − | * The purpose of this design is to reduce the amount of heat transferred between the lip and the rest of the body.
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| − | * By reducing heat transfer, the shadow ring can help maintain the desired temperature within the processing chamber.
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| − | * This innovation can improve the efficiency and effectiveness of semiconductor processing.
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| − |
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| − | '''Abstract'''
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| − | A shadow ring for a processing chamber, such as a semiconductor processing chamber, is an annular member including a body with a radially inwardly projecting lip. The shadow ring includes a feature that mitigates heat transfer between the lip and the rest of the body. In one example, the feature includes a plurality of apertures, each aperture extending from an upper opening at an upper surface of the shadow ring to a corresponding lower opening at a lower surface of the shadow ring. A neck between adjacent apertures creates a bottleneck that hinders conductive heat transfer.
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| | | | |
| | ===RF MEASUREMENT FROM A TRANSMISSION LINE SENSOR ([[US Patent Application 17737682. RF MEASUREMENT FROM A TRANSMISSION LINE SENSOR simplified abstract|17737682]])=== | | ===RF MEASUREMENT FROM A TRANSMISSION LINE SENSOR ([[US Patent Application 17737682. RF MEASUREMENT FROM A TRANSMISSION LINE SENSOR simplified abstract|17737682]])=== |
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| | David Coumou | | David Coumou |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a sensor that includes a board with an aperture, a current loop winding through the board around the aperture, and a voltage ring around the aperture within the current loop.
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| − | * The sensor has a board with a hole in it.
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| − | * There is a loop of current that goes through the board around the hole.
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| − | * There is also a ring of voltage around the hole, inside the current loop.
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| − | * The voltage ring consists of an interior ring, an insulator ring around the interior ring, and an exterior ring around the insulator ring.
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| − |
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| − | '''Abstract'''
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| − | Embodiments disclosed herein include a sensor. In an embodiment, the sensor comprises a board, wherein an aperture is formed through the board, a current loop winding through the board around the aperture, and a voltage ring around the aperture and within an inner perimeter of the current loop, wherein the voltage ring comprises an interior ring, an insulator ring around the interior ring, and an exterior ring around the insulator ring.
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| | ===METHODS AND MECHANISMS FOR ADJUSTING FILM DEPOSITION PARAMETERS DURING SUBSTRATE MANUFACTURING ([[US Patent Application 17737318. METHODS AND MECHANISMS FOR ADJUSTING FILM DEPOSITION PARAMETERS DURING SUBSTRATE MANUFACTURING simplified abstract|17737318]])=== | | ===METHODS AND MECHANISMS FOR ADJUSTING FILM DEPOSITION PARAMETERS DURING SUBSTRATE MANUFACTURING ([[US Patent Application 17737318. METHODS AND MECHANISMS FOR ADJUSTING FILM DEPOSITION PARAMETERS DURING SUBSTRATE MANUFACTURING simplified abstract|17737318]])=== |
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| | Mitesh Sanghvi | | Mitesh Sanghvi |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes an electronic device manufacturing system that collects data about a deposition process performed on a substrate. This process creates multiple layers on the substrate's surface.
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| − |
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| − | * The system also obtains an expected profile for the process, which includes desired thickness values for each layer.
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| − | * Using the collected data and the expected profile, the system generates a correction profile. This correction profile includes a deposition time offset value for at least one layer.
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| − | * The system then creates an updated process recipe by applying the correction profile to the original process recipe.
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| − | * Finally, the system performs a deposition step on the substrate based on the updated process recipe.
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| − |
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| − | '''Abstract'''
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| − | An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.
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| | ===HIGH BANDWIDTH ARCHITECTURE FOR CENTRALIZED COHERENT CONTROL AT THE EDGE OF PROCESSING TOOL ([[US Patent Application 17737659. HIGH BANDWIDTH ARCHITECTURE FOR CENTRALIZED COHERENT CONTROL AT THE EDGE OF PROCESSING TOOL simplified abstract|17737659]])=== | | ===HIGH BANDWIDTH ARCHITECTURE FOR CENTRALIZED COHERENT CONTROL AT THE EDGE OF PROCESSING TOOL ([[US Patent Application 17737659. HIGH BANDWIDTH ARCHITECTURE FOR CENTRALIZED COHERENT CONTROL AT THE EDGE OF PROCESSING TOOL simplified abstract|17737659]])=== |
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| | David Coumou | | David Coumou |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a processing tool that includes a power supply, an impedance matching network, a cathode, and a processing module.
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| − | * The processing tool is designed to supply power to the cathode through the impedance matching network.
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| − | * The processing module is connected to both the power supply and the impedance matching network.
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| − | * The purpose of the processing tool is not specified in the abstract.
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| − |
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| − | '''Abstract'''
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| − | Embodiments disclosed herein include a processing tool. In an embodiment, the processing tool comprises a power supply, an impedance matching network coupled to the power supply, a cathode, wherein the power supply is configured to supply power through the impedance matching network to the cathode, and a processing module, wherein the processing module is communicatively coupled to the power supply and the impedance matching network.
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| | | | |
| | ===CONTROL AND PREDICTION OF MULTIPLE PLASMA COUPLING SURFACES AND CORRESPONDING POWER TRANSFER ([[US Patent Application 17737670. CONTROL AND PREDICTION OF MULTIPLE PLASMA COUPLING SURFACES AND CORRESPONDING POWER TRANSFER simplified abstract|17737670]])=== | | ===CONTROL AND PREDICTION OF MULTIPLE PLASMA COUPLING SURFACES AND CORRESPONDING POWER TRANSFER ([[US Patent Application 17737670. CONTROL AND PREDICTION OF MULTIPLE PLASMA COUPLING SURFACES AND CORRESPONDING POWER TRANSFER simplified abstract|17737670]])=== |
| Line 252: |
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| | David Coumou | | David Coumou |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a process power controller for a plasma processing tool.
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| − |
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| − | * The process power controller includes a process power source optimizer, a source predictor, and a process uniformity controller.
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| − | * The source predictor is connected to both the process power source optimizer and the process uniformity controller.
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| − | * The process power controller is designed to optimize the power source for the plasma processing tool.
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| − | * The source predictor helps in predicting the power requirements for the process.
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| − | * The process uniformity controller ensures that the process is carried out uniformly.
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| − | * The process power controller improves the efficiency and effectiveness of the plasma processing tool.
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| − |
| |
| − | '''Abstract'''
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| − | Embodiments disclosed herein include a process power controller for a plasma processing tool. In an embodiment, the process power controller includes a process power source optimizer, a source predictor, and a process uniformity controller. In an embodiment, the source predictor is communicatively coupled to the process power source optimizer and the process uniformity controller.
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| | | | |
| | ===OPTICAL DEVICE IMPROVEMENT ([[US Patent Application 18131997. OPTICAL DEVICE IMPROVEMENT simplified abstract|18131997]])=== | | ===OPTICAL DEVICE IMPROVEMENT ([[US Patent Application 18131997. OPTICAL DEVICE IMPROVEMENT simplified abstract|18131997]])=== |
| Line 273: |
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| | Yue CHEN | | Yue CHEN |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for processing an optical device using plasma technology.
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| − |
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| − | * The method involves positioning the optical device on a substrate support within a process chamber.
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| − | * The optical device consists of an optical device substrate and multiple optical device structures.
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| − | * Each optical device structure is composed of a bulk region made of silicon carbide and one or more surface regions made of silicon oxycarbide.
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| − | * Process gases are introduced into the process chamber, and a plasma is generated within the chamber for a specific duration while the optical device is on the substrate support.
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| − | * After the first time period, the plasma is stopped.
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| − | * The plasma treatment reduces the carbon content of the surface regions of each optical device structure by at least 50%.
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| − |
| |
| − | '''Abstract'''
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| − | A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.
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| | | | |
| | ===TEMPERATURE AND BIAS CONTROL OF EDGE RING ([[US Patent Application 18356915. TEMPERATURE AND BIAS CONTROL OF EDGE RING simplified abstract|18356915]])=== | | ===TEMPERATURE AND BIAS CONTROL OF EDGE RING ([[US Patent Application 18356915. TEMPERATURE AND BIAS CONTROL OF EDGE RING simplified abstract|18356915]])=== |
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| | James ROGERS | | James ROGERS |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application describes methods and apparatus for controlling the processing result profile near the edge of a substrate during plasma-assisted processing.
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| − | - The substrate support assembly includes a first base plate and a second base plate, both of which have cooling mechanisms.
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| − | - The assembly also includes a substrate support and a biasing ring, both made of a dielectric material.
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| − | - An edge ring biasing electrode is embedded in the dielectric material of the biasing ring.
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| − | - An edge ring is placed on the biasing ring.
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| − | - The purpose of this invention is to improve the control and uniformity of processing near the edge of a substrate during plasma-assisted processing.
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| − |
| |
| − | '''Abstract'''
| |
| − | Embodiments described herein provide methods and apparatus used to control a processing result profile proximate to a circumferential edge of a substrate during the plasma-assisted processing thereof. In one embodiment, a substrate support assembly features a first base plate and a second base plate circumscribing the first base plate. The first and second base plates each have one or more respective first and second cooling disposed therein. The substrate support assembly further features a substrate support disposed on and thermally coupled to the first base plate, and a biasing ring disposed on and thermally coupled to the second base plate. Here, the substrate support and the biasing ring are each formed of a dielectric material. The substrate support assembly further includes an edge ring biasing electrode embedded in the dielectric material of the biasing ring and an edge ring disposed on the biasing ring.
| |
| | | | |
| | ===AUTONOMOUS FREQUENCY RETRIEVAL FROM PLASMA POWER SOURCES ([[US Patent Application 17737665. AUTONOMOUS FREQUENCY RETRIEVAL FROM PLASMA POWER SOURCES simplified abstract|17737665]])=== | | ===AUTONOMOUS FREQUENCY RETRIEVAL FROM PLASMA POWER SOURCES ([[US Patent Application 17737665. AUTONOMOUS FREQUENCY RETRIEVAL FROM PLASMA POWER SOURCES simplified abstract|17737665]])=== |
| Line 313: |
Line 120: |
| | David Coumou | | David Coumou |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a processing tool that includes various components for analyzing transmission lines.
| |
| − | * The processing tool includes a transmission line sensor and an analog to digital converter.
| |
| − | * It may also include a digital down converter and a frequency digital phase lock loop.
| |
| − | * Additionally, the processing tool may have a transmission line scaling module.
| |
| − | * The purpose of the tool is to process and analyze data from transmission lines.
| |
| − | * The transmission line sensor detects signals from the transmission lines and converts them to digital format using the analog to digital converter.
| |
| − | * The digital down converter and frequency digital phase lock loop help in further processing and analysis of the signals.
| |
| − | * The transmission line scaling module is used to adjust the scaling of the transmission line data for accurate analysis.
| |
| − | * Overall, the processing tool provides a comprehensive solution for analyzing transmission lines.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Embodiments disclosed herein include a processing tool. In an embodiment the processing tool comprises a transmission line sensor, and an analog to digital (A/D) converter. In an embodiment, the processing tool may further comprise a digital down converter (DDC), and a frequency digital phase lock loop (dPLL). In an embodiment, the processing tool may further comprise a transmission line scaling module.
| |
| | | | |
| | ===LARGE AREA GAPFILL USING VOLUMETRIC EXPANSION ([[US Patent Application 17737340. LARGE AREA GAPFILL USING VOLUMETRIC EXPANSION simplified abstract|17737340]])=== | | ===LARGE AREA GAPFILL USING VOLUMETRIC EXPANSION ([[US Patent Application 17737340. LARGE AREA GAPFILL USING VOLUMETRIC EXPANSION simplified abstract|17737340]])=== |
| Line 335: |
Line 128: |
| | Supriya Ghosh | | Supriya Ghosh |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes methods of semiconductor processing using a silicon-containing precursor.
| |
| − | - A substrate is placed in a semiconductor processing chamber and has features on its surface.
| |
| − | - A silicon-containing material is deposited on the substrate, extending into the features.
| |
| − | - An oxygen-containing precursor is introduced.
| |
| − | - The silicon-containing material is annealed with the oxygen-containing precursor, causing it to expand within the features.
| |
| − | - The process can be repeated to fill the features on the substrate.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.
| |
| | | | |
| | ===SILICON-AND-CARBON-CONTAINING MATERIALS WITH LOW DIELECTRIC CONSTANTS ([[US Patent Application 17737328. SILICON-AND-CARBON-CONTAINING MATERIALS WITH LOW DIELECTRIC CONSTANTS simplified abstract|17737328]])=== | | ===SILICON-AND-CARBON-CONTAINING MATERIALS WITH LOW DIELECTRIC CONSTANTS ([[US Patent Application 17737328. SILICON-AND-CARBON-CONTAINING MATERIALS WITH LOW DIELECTRIC CONSTANTS simplified abstract|17737328]])=== |
| Line 354: |
Line 136: |
| | Zeqing Shen | | Zeqing Shen |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a method for semiconductor processing using silicon and carbon precursors.
| |
| − | - The carbon-containing precursor used in the method has a carbon-carbon double bond or a carbon-carbon triple bond.
| |
| − | - A substrate is placed in a semiconductor processing chamber.
| |
| − | - An oxygen-containing precursor is introduced into the chamber.
| |
| − | - The silicon-containing precursor, carbon-containing precursor, and oxygen-containing precursor are thermally reacted at a temperature below 700°C.
| |
| − | - This reaction results in the formation of a silicon-and-carbon-containing layer on the substrate.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the oxygen-containing precursor at a temperature less than or about 700° C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.
| |
| | | | |
| | ===PULSED ETCH PROCESS ([[US Patent Application 17738526. PULSED ETCH PROCESS simplified abstract|17738526]])=== | | ===PULSED ETCH PROCESS ([[US Patent Application 17738526. PULSED ETCH PROCESS simplified abstract|17738526]])=== |
| Line 373: |
Line 144: |
| | Yifeng Zhou | | Yifeng Zhou |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a method for etching a sample using a plasma etch pulse.
| |
| − | - The method involves directing a gas flow containing silicon tetrachloride (SiCl) and a diluent towards the sample.
| |
| − | - During the gas flow, a bias power is applied for a certain period of time to achieve a bias state.
| |
| − | - Then, a source power is applied for another period of time to achieve a source state.
| |
| − | - After that, no bias power and no source power are applied for a certain period of time to achieve a recovery state.
| |
| − | - This plasma etch pulse is repeated until a desired amount of the sample is etched.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Described herein is a method for etching a sample. The method includes performing a plasma etch pulse. The plasma etch pulse is performed by directing a gas flow comprising silicon tetrachloride (SiCl) and a diluent towards the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first time period. Then, a source power is applied to achieve a source state for a second time period, and then no bias power and no source power is applied to achieve a recovery state for a third time period. The plasma etch pulse is repeated until a target amount of the sample is etched.
| |
| | | | |
| | ===LOW TEMPERATURE CARBON GAPFILL ([[US Patent Application 17737311. LOW TEMPERATURE CARBON GAPFILL simplified abstract|17737311]])=== | | ===LOW TEMPERATURE CARBON GAPFILL ([[US Patent Application 17737311. LOW TEMPERATURE CARBON GAPFILL simplified abstract|17737311]])=== |
| Line 392: |
Line 152: |
| | Supriya Ghosh | | Supriya Ghosh |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for semiconductor processing using a carbon-containing precursor.
| |
| − |
| |
| − | * The method involves introducing a carbon-containing precursor into a semiconductor processing chamber.
| |
| − | * A substrate is placed in the chamber, which has features on its surface.
| |
| − | * A plasma of the carbon-containing precursor is formed in the chamber.
| |
| − | * The carbon-containing material is deposited on the substrate, extending into the features.
| |
| − | * A plasma of a hydrogen-containing precursor is then formed in the chamber.
| |
| − | * The carbon-containing material is treated with the plasma effluents of the hydrogen-containing precursor.
| |
| − | * This treatment causes some of the carbon-containing material to be removed from the substrate.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Exemplary methods of semiconductor processing may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include forming a plasma of the carbon-containing precursor within the processing region. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more features along the substrate. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include treating the carbon-containing material with plasma effluents of the hydrogen-containing precursor. The plasma effluents of the hydrogen-containing precursor may cause a portion of the carbon-containing material to be removed from the substrate.
| |
| | | | |
| | ===WAFER FILM FRAME CARRIER ([[US Patent Application 17735623. WAFER FILM FRAME CARRIER simplified abstract|17735623]])=== | | ===WAFER FILM FRAME CARRIER ([[US Patent Application 17735623. WAFER FILM FRAME CARRIER simplified abstract|17735623]])=== |
| Line 414: |
Line 160: |
| | Jason A. Rye | | Jason A. Rye |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor substrate carrier frame that has a central aperture and multiple fingers attached to the frame body. Each finger extends into the central aperture and has a substrate receiving interface. One or more of the fingers have an actuator that can manipulate the finger between a substrate holding position and an open position.
| |
| − |
| |
| − | * The patent application is for a semiconductor substrate carrier frame.
| |
| − | * The frame has a central aperture and multiple fingers attached to it.
| |
| − | * Each finger extends into the central aperture and has a substrate receiving interface.
| |
| − | * Some of the fingers have an actuator that can manipulate them between holding a substrate and being open.
| |
| − | * The innovation allows for efficient handling and manipulation of semiconductor substrates.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Exemplary semiconductor substrate carrier frames may include a frame body defining a central aperture. The frames may include a plurality of fingers that are coupled with the frame body. Each of the plurality of fingers may extend into the central aperture. Each of the plurality of fingers may include a substrate receiving interface. At least one of the plurality of fingers may include an actuator that manipulates a respective one of the at least one of the plurality of fingers between a substrate holding position and an open position.
| |
| | | | |
| | ===COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING ([[US Patent Application 18356553. COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING simplified abstract|18356553]])=== | | ===COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING ([[US Patent Application 18356553. COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING simplified abstract|18356553]])=== |
| Line 434: |
Line 168: |
| | Jason M. SCHALLER | | Jason M. SCHALLER |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a process chamber with coaxial lift devices.
| |
| − | - The device includes a bottom bowl lift and a pedestal lift.
| |
| − | - The bottom bowl lift moves the bottom bowl to reduce the process volume.
| |
| − | - The bottom bowl lift and the pedestal lift are attached for vacuum operation.
| |
| − | - The pedestal lift has multiple actuators to create a dynamic lift mechanism.
| |
| − | - The bottom bowl lift is adjustable and can close the bottom bowl to create a small process volume.
| |
| − | - The pedestal lift can move independently and tilt in a desired direction without interference from the bottom bowl lift.
| |
| − | - This increases film uniformity on a processed substrate.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Embodiments described herein generally relate to process chambers with coaxial lift devices. In some embodiments, the device comprises both a bottom bowl lift and a pedestal lift. The bottom bowl lift supports a bottom bowl and is configured to move the bottom bowl into a position that reduces the process volume. The bottom bowl lift is co-axial with the pedestal lift and the bottom bowl lift and the pedestal lift are attached for vacuum operation. The pedestal lift includes multiple actuators to create a dynamic lift mechanism. Both systems complete a nested system such that the bottom bowl lift is adjustable and can close the bottom bowl creating a symmetric and small process volume. The pedestal lift can move independently to its process position and tilt in a desired direction without interference with the bottom bowl lift, increasing film uniformity on a processed substrate.
| |
| | | | |
| | ===COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING ([[US Patent Application 18356579. COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING simplified abstract|18356579]])=== | | ===COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING ([[US Patent Application 18356579. COAXIAL LIFT DEVICE WITH DYNAMIC LEVELING simplified abstract|18356579]])=== |
| Line 455: |
Line 176: |
| | Jason M. SCHALLER | | Jason M. SCHALLER |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a process chamber with coaxial lift devices.
| |
| − | - The device includes a bottom bowl lift and a pedestal lift.
| |
| − | - The bottom bowl lift moves the bottom bowl into a position that reduces the process volume.
| |
| − | - The bottom bowl lift and the pedestal lift are attached for vacuum operation.
| |
| − | - The pedestal lift has multiple actuators to create a dynamic lift mechanism.
| |
| − | - The bottom bowl lift is adjustable and can close the bottom bowl, creating a symmetric and small process volume.
| |
| − | - The pedestal lift can move independently to its process position and tilt in a desired direction without interference from the bottom bowl lift.
| |
| − | - This innovation improves film uniformity on a processed substrate.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Embodiments described herein generally relate to process chambers with coaxial lift devices. In some embodiments, the device comprises both a bottom bowl lift and a pedestal lift. The bottom bowl lift supports a bottom bowl and is configured to move the bottom bowl into a position that reduces the process volume. The bottom bowl lift is co-axial with the pedestal lift and the bottom bowl lift and the pedestal lift are attached for vacuum operation. The pedestal lift includes multiple actuators to create a dynamic lift mechanism. Both systems complete a nested system such that the bottom bowl lift is adjustable and can close the bottom bowl creating a symmetric and small process volume. The pedestal lift can move independently to its process position and tilt in a desired direction without interference with the bottom bowl lift, increasing film uniformity on a processed substrate.
| |
| | | | |
| | ===SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS ([[US Patent Application 18224861. SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS simplified abstract|18224861]])=== | | ===SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS ([[US Patent Application 18224861. SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS simplified abstract|18224861]])=== |
| Line 476: |
Line 184: |
| | Suketu Arun PARIKH | | Suketu Arun PARIKH |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes a method for etching a metal containing feature.
| |
| − | - A pattern mask is used to etch layers of material and expose a portion of the metal containing feature.
| |
| − | - The exposed portion of the metal containing feature is etched and replaced by the growth of a filler dielectric.
| |
| − | - This process helps reduce unwanted conductivity between adjacent metal containing features.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.
| |
| | | | |
| | ===CONFORMAL METAL DICHALCOGENIDES ([[US Patent Application 17739856. CONFORMAL METAL DICHALCOGENIDES simplified abstract|17739856]])=== | | ===CONFORMAL METAL DICHALCOGENIDES ([[US Patent Application 17739856. CONFORMAL METAL DICHALCOGENIDES simplified abstract|17739856]])=== |
| Line 493: |
Line 192: |
| | Chandan Das | | Chandan Das |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application describes transition metal dichalcogenide films and methods for depositing them on a substrate.
| |
| − | - It also describes methods for converting transition metal oxide films to transition metal dichalcogenide films.
| |
| − | - The process involves exposing the substrate to a metal precursor and an oxidant to form a transition metal oxide film.
| |
| − | - Then, the transition metal oxide film is exposed to a chalcogenide precursor to form the transition metal dichalcogenide film.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Transition metal dichalcogenide films and methods for depositing transition metal dichalcogenide films on a substrate are described. Methods for converting transition metal oxide films to transition metal dichalcogenide films are also described. The substrate is exposed to a metal precursor and an oxidant to form a transition metal oxide film; the transition metal oxide film is exposed to a chalcogenide precursor to form the transition metal dichalcogenide film.
| |
| | | | |
| | ===DRY TREATMENT FOR SURFACE LOSS REMOVAL IN MICRO-LED STRUCTURES ([[US Patent Application 17736843. DRY TREATMENT FOR SURFACE LOSS REMOVAL IN MICRO-LED STRUCTURES simplified abstract|17736843]])=== | | ===DRY TREATMENT FOR SURFACE LOSS REMOVAL IN MICRO-LED STRUCTURES ([[US Patent Application 17736843. DRY TREATMENT FOR SURFACE LOSS REMOVAL IN MICRO-LED STRUCTURES simplified abstract|17736843]])=== |
| Line 510: |
Line 200: |
| | Michel Khoury | | Michel Khoury |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | - The patent application is about a method to correct defects in microLED structures caused by a mesa etch process.
| |
| − | - The defects decrease the efficiency of the microLEDs.
| |
| − | - The method involves a dry etch process that removes the surface layers of the microLED structures with defects.
| |
| − | - The dry etch process incrementally removes a small outer layer to preserve the overall shape of the microLED structures.
| |
| − | - The resulting surface is smooth and suitable for the application of a dielectric layer.
| |
| − | - The dry etch process consists of two steps that are repeated: a first gas reacts with the surface to form a gallium compound layer, and a second gas selectively removes that layer.
| |
| − | - The dry etch process can be plasma-based or reactive thermal etches.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A mesa etch may form the geometry of microLED structures. However, the mesa etch may induce defects in the microLED structures that decreases the efficiency of the microLEDs. To correct these defects, a dry etch process may be performed that incrementally removes the surface layers of the microLED structures with the defects. The dry etch may be configured to incrementally remove a small outer layer, and thus may preserve the overall shape of the microLED structures while leaving a smooth surface for the application of a dielectric layer. The dry etch process may include two steps that are repeatedly performed. A first gas may react with the surface to form a gallium compound layer, and a second gas may then selectively remove that layer. The dry etch may include plasma-based etches or reactive thermal etches.
| |
| | | | |
| | ===IMPEDANCE TUNING UTILITY OF VECTOR SPACE DEFINED BY TRANSMISSION LINE QUANTITIES ([[US Patent Application 17737677. IMPEDANCE TUNING UTILITY OF VECTOR SPACE DEFINED BY TRANSMISSION LINE QUANTITIES simplified abstract|17737677]])=== | | ===IMPEDANCE TUNING UTILITY OF VECTOR SPACE DEFINED BY TRANSMISSION LINE QUANTITIES ([[US Patent Application 17737677. IMPEDANCE TUNING UTILITY OF VECTOR SPACE DEFINED BY TRANSMISSION LINE QUANTITIES simplified abstract|17737677]])=== |
| Line 529: |
Line 207: |
| | | | |
| | David Coumou | | David Coumou |
| − |
| |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for impedance tuning in a semiconductor processing tool.
| |
| − | * The method involves measuring the voltage and current of a transmission line.
| |
| − | * The measured analog voltage and current signals are converted into digital signals.
| |
| − | * A u-vector is calculated from the digital voltage and current signals.
| |
| − | * The real components of the u-vector are used to calculate the position of a first capacitor (C1).
| |
| − | * The imaginary components of the u-vector are used to calculate the position of a second capacitor (C2).
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool. In an embodiment, the method comprises measuring a voltage and a current of a transmission line, converting an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal, calculating a u-vector from the digital voltage signal and the digital current signal, calculating a C1 position of a first capacitor with real components of the u-vector, and calculating a C2 position of a second capacitor with imaginary components of the u-vector.
| |
