18538458. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Yun Seok Choi of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18538458 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the patent application includes an upper substrate with a semiconductor chip, a buffer layer, a mold layer, through-electrodes, an interconnection layer, and bumps. The mold layer has a coefficient of thermal expansion greater than that of the upper substrate.

  • The semiconductor package includes:
    • Upper substrate with first and second surfaces
    • Semiconductor chip on the first surface
    • Buffer layer on the second surface
    • Mold layer between the second surface and the buffer layer
    • Through-electrodes penetrating the upper substrate and mold layer
    • Interconnection layer connecting the semiconductor chip to the through-electrodes
    • Bumps on the buffer layer connected to the through-electrodes

Potential Applications

The technology described in the patent application could be used in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics.

Problems Solved

This technology helps in improving the thermal expansion matching between different layers of the semiconductor package, reducing the risk of delamination and improving the overall reliability of the package.

Benefits

The semiconductor package design described in the patent application offers improved reliability, better thermal performance, and potentially longer lifespan for electronic devices.

Potential Commercial Applications

The technology could be applied in the manufacturing of semiconductor packages for a wide range of electronic devices, potentially leading to more reliable and durable products.

Possible Prior Art

One possible prior art could be the use of different materials with varying coefficients of thermal expansion in semiconductor packages to address issues related to thermal stress and reliability.

Unanswered Questions

How does the coefficient of thermal expansion impact the overall performance of the semiconductor package?

The article does not delve into the specific effects of the coefficient of thermal expansion on the performance of the semiconductor package.

What are the specific electronic devices that could benefit the most from this technology?

The article does not provide information on the specific electronic devices that could benefit the most from the technology described in the patent application.


Original Abstract Submitted

A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.