18527978. NAND DATA PLACEMENT SCHEMA simplified abstract (Micron Technology, Inc.)
Contents
- 1 NAND DATA PLACEMENT SCHEMA
NAND DATA PLACEMENT SCHEMA
Organization Name
Inventor(s)
Carminantonio Manganelli of Benevento (IT)
Massimo Iaculo of San Marco Evangelista (IT)
Giuseppe D'eliseo of Caserta (IT)
Alberto Sassara of Napoli (IT)
NAND DATA PLACEMENT SCHEMA - A simplified explanation of the abstract
This abstract first appeared for US patent application 18527978 titled 'NAND DATA PLACEMENT SCHEMA
Simplified Explanation
The present disclosure describes improvements to data placement architectures in NAND that enhance data protection through a diagonal striping schema and storing parity bits in SLC blocks.
- Diagonal striping of data across page lines and planes
- Storing parity bits in SLC blocks for extra protection
- Deleting parity bits after block is finished writing
Potential Applications
The technology described in this patent application could be applied in:
- Solid-state drives (SSDs)
- Data centers
- Embedded systems
Problems Solved
This technology addresses the following issues:
- Data loss in NAND due to failure scenarios
- Ensuring data integrity during write operations
Benefits
The benefits of this technology include:
- Enhanced data protection
- Improved recovery from failure scenarios
- Increased reliability of NAND storage
Potential Commercial Applications
A potential commercial application for this technology could be in:
- Enterprise storage solutions
- Consumer electronics
- Cloud computing services
Possible Prior Art
One possible prior art related to this technology is the use of error correction codes (ECC) in NAND storage to detect and correct errors in data.
What are the specific failure scenarios that this technology aims to address?
This technology aims to address failure scenarios such as data corruption during write operations and block failures in NAND storage.
How does the diagonal striping of data across page lines and planes enhance data protection?
The diagonal striping of data helps distribute the data more evenly across the NAND storage, reducing the likelihood of data loss in case of a failure in a specific block or plane.
Original Abstract Submitted
Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.
