18519872. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Kioxia Corporation)

SEMICONDUCTOR MEMORY DEVICE

Organization Name

Kioxia Corporation

Inventor(s)

Yoshiaki Fukuzumi of Yokkaichi (JP)

Hideaki Aochi of Yokkaichi (JP)

Mie Matsuo of Yokkaichi (JP)

Kenichiro Yoshii of Bunkyo (JP)

Koichiro Shindo of Yokohama (JP)

Kazushige Kawasaki of Kawasaki (JP)

Tomoya Sanuki of Yokkaichi (JP)

SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18519872 titled 'SEMICONDUCTOR MEMORY DEVICE

Simplified Explanation

The patent application describes a technology where an array chip and a circuit chip are connected using a bonding metal between their interconnection layers.

• Three-dimensionally disposed memory cells in the array chip
• Memory-side interconnection layer connected to memory cells
• Control circuit on the substrate of the circuit chip
• Circuit-side interconnection layer on the control circuit
• Bonding metal between memory-side and circuit-side interconnection layers

Potential Applications

This technology could be applied in:

• High-performance computing systems
• Data storage devices
• Embedded systems

Problems Solved

This technology helps in:

• Improving data transfer speeds
• Enhancing memory chip integration
• Increasing overall system efficiency

Benefits

The benefits of this technology include:

• Faster data processing
• Compact chip design
• Reliable interconnection between chips

Potential Commercial Applications

This technology could be commercially used in:

• Smartphones and tablets
• Servers and data centers
• Automotive electronics

Possible Prior Art

One possible prior art for this technology could be the use of bonding metals in semiconductor packaging to improve chip connectivity.

How does this technology impact power consumption in electronic devices?

This article does not address the specific impact of this technology on power consumption in electronic devices.

What are the potential challenges in scaling up this technology for mass production?

The article does not discuss the potential challenges in scaling up this technology for mass production.

Original Abstract Submitted

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.