18518187. Integrated Circuit Package and Method simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
Integrated Circuit Package and Method
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Wen-Chih Chiou of Zhunan Township (TW)
Integrated Circuit Package and Method - A simplified explanation of the abstract
This abstract first appeared for US patent application 18518187 titled 'Integrated Circuit Package and Method
Simplified Explanation
The patent application describes a device package consisting of two dies bonded together with a conductor-to-conductor bond at an interface, surrounded by an encapsulant with through vias and thermal vias, and connected to a redistribution structure.
- Two dies are bonded together with a conductor-to-conductor bond at an interface.
- The package includes an encapsulant surrounding the dies with through vias adjacent to them.
- A plurality of thermal vias is present on the surface of the second die, adjacent to the first die.
- The redistribution structure is electrically connected to the dies and through vias.
Potential Applications
- Semiconductor packaging
- Microelectronics
- Integrated circuits
Problems Solved
- Improved thermal management
- Enhanced electrical connectivity
- Increased reliability of the device package
Benefits
- Better heat dissipation
- Enhanced electrical performance
- Increased durability and longevity of the device package
Original Abstract Submitted
A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
