18517330. BUFFER DESIGN FOR PACKAGE INTEGRATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
BUFFER DESIGN FOR PACKAGE INTEGRATION
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Jie Chen of New Taipei City (TW)
Hsien-Wei Chen of Hsinchu (TW)
Ming-Fa Chen of Taichung City (TW)
BUFFER DESIGN FOR PACKAGE INTEGRATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18517330 titled 'BUFFER DESIGN FOR PACKAGE INTEGRATION
Simplified Explanation
The method described in the patent application involves bonding a device die to an interposer wafer, which includes metal lines and vias. A dielectric region is formed around the device die, and a through-via is created to pass through the dielectric region. The through-via is connected to the device die through the metal lines and vias in the interposer wafer. A polymer layer is then formed over the dielectric region, and an electrical connector is established. The electrical connector is linked to the through-via through a conductive feature in the polymer layer. Finally, the interposer wafer is sawed to separate the package from others.
- Bonding a device die to an interposer wafer with metal lines and vias
- Forming a dielectric region around the device die
- Creating a through-via to connect the device die electrically
- Applying a polymer layer over the dielectric region
- Establishing an electrical connector linked to the through-via
- Sawing the interposer wafer to separate the package
Potential Applications
- Semiconductor packaging
- Microelectronics
- Integrated circuits
Problems Solved
- Enhanced electrical connectivity
- Improved signal transmission
- Miniaturization of electronic devices
Benefits
- Increased reliability
- Higher performance
- Cost-effective manufacturing process
Original Abstract Submitted
A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.
