18508663. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Eunseok Song of Hwaseong-si (KR)
Keung Beum Kim of Hwaseong-si (KR)
Kyung Suk Oh of Seongnam-si (KR)
Eon Soo Jang of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18508663 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a first semiconductor chip with a logic structure and a second semiconductor chip bonded to it. The first chip has signal lines on one surface connected to the logic structure, a power delivery network on the opposite surface, and penetration vias connecting the power delivery network to the logic structure. The second chip has a capacitor layer adjacent to the power delivery network.
- First semiconductor chip with logic structure
- Second semiconductor chip bonded to the first chip
- Signal lines on the first chip connected to logic structure
- Power delivery network on the first chip's opposite surface
- Penetration vias connecting power delivery network to logic structure
- Second chip with capacitor layer adjacent to power delivery network
Potential Applications
- Advanced electronics manufacturing
- Semiconductor packaging industry
- Integrated circuit design
Problems Solved
- Efficient power delivery in semiconductor packages
- Improved signal integrity
- Enhanced performance of semiconductor chips
Benefits
- Higher reliability in semiconductor devices
- Increased functionality in compact packages
- Enhanced overall performance of electronic systems
Original Abstract Submitted
A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.
