18388342. MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS simplified abstract (Micron Technology, Inc.)
MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS
Organization Name
Inventor(s)
Tingjun Xie of Milpitas CA (US)
Zhenming Zhou of San Jose CA (US)
Charles Kwong of Redwood City CA (US)
MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18388342 titled 'MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS
Simplified Explanation
The processing device of a memory sub-system is designed to perform multiple write operations on a memory device with multiple memory units. The device maintains state information of the memory device after each write operation, identifies a memory unit that has been written to by a certain threshold of write operations, and refreshes data stored in memory units near the identified unit if certain criteria are met.
- The processing device performs multiple write operations on a memory device with multiple memory units.
- State information of the memory device is maintained after each write operation.
- A memory unit that has been written to by a threshold fraction of write operations is identified.
- Data stored in memory units near the identified unit is refreshed if specific criteria are satisfied.
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- Potential Applications
- Data storage systems
- Memory management in computer systems
- Embedded systems
- Problems Solved
- Efficient memory management
- Preventing data corruption
- Optimizing memory refresh processes
- Benefits
- Improved data reliability
- Enhanced memory performance
- Extended memory device lifespan
Original Abstract Submitted
A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units, the processing device is configured to maintain state information of the memory device in response to performing each write operation of a plurality of write operations on the memory device; identify, in view of the state information, a candidate memory unit of the plurality of memory units that has been written to by at least a threshold fraction of the plurality of write operations performed on the memory device; and responsive to determining that a number of write operations performed on the memory device satisfies a threshold refresh criterion and that one or more of the plurality of memory units that are proximate to the candidate memory unit satisfy a failed bit threshold criterion, refresh data stored at the one or more of the plurality of memory units that are proximate to the candidate memory unit.
