18383370. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP VIA SUBSTRATE CONTACTS FOR SUB-FIN ELECTRICAL CONTACT simplified abstract (Intel Corporation)

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP VIA SUBSTRATE CONTACTS FOR SUB-FIN ELECTRICAL CONTACT

Organization Name

Intel Corporation

Inventor(s)

Biswajeet Guha of Hillsboro OR (US)

William Hsu of Hillsboro OR (US)

Chung-Hsun Lin of Portland OR (US)

Kinyip Phoa of Beaverton OR (US)

Oleg Golonzka of Beaverton OR (US)

Tahir Ghani of Portland OR (US)

Kalyan Kolluru of Portland OR (US)

Nathan Jack of Forest Grove OR (US)

Nicholas Thomson of Hillsboro OR (US)

Ayan Kar of Portland OR (US)

Benjamin Orr of Munich (DE)

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP VIA SUBSTRATE CONTACTS FOR SUB-FIN ELECTRICAL CONTACT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18383370 titled 'GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP VIA SUBSTRATE CONTACTS FOR SUB-FIN ELECTRICAL CONTACT

Simplified Explanation

The abstract describes gate-all-around integrated circuit structures with adjacent deep via substrate contact for sub-fin electrical contact.

• Conductive via on a semiconductor substrate
• Vertical arrangement of horizontal nanowires above a fin protruding from the semiconductor substrate
• Channel region of the nanowires electrically isolated from the fin
• Fin electrically coupled to the conductive via
• Gate stack over the nanowires

• • Potential Applications:**

- Advanced semiconductor devices - High-performance integrated circuits - Nanoelectronics

• • Problems Solved:**

- Improved electrical contact in sub-fin regions - Enhanced performance and functionality of integrated circuits - Increased efficiency in semiconductor device manufacturing

• • Benefits:**

- Enhanced electrical connectivity - Improved device performance - Increased integration density - Enhanced reliability and stability of integrated circuits

Original Abstract Submitted

Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.