18322040. HIGHLY VERTICALLY INTEGRATED NONVOLATILE MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
HIGHLY VERTICALLY INTEGRATED NONVOLATILE MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
Organization Name
Inventor(s)
Seungyeon Kim of Suwon-si (KR)
HIGHLY VERTICALLY INTEGRATED NONVOLATILE MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18322040 titled 'HIGHLY VERTICALLY INTEGRATED NONVOLATILE MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
Simplified Explanation
The abstract describes a vertically-integrated nonvolatile memory device that consists of a peripheral circuit structure and a cell array structure. The cell array structure is bonded to the peripheral circuit structure and includes a cell area and a connection area. The cell area contains multiple gate electrodes and insulating layers stacked alternately. The gate electrodes have a staircase shape and are connected to a cell stack. The connection area includes capacitor core contact structures that pass through the cell stack and capacitor gate contact structures connected to the gate electrodes. Each capacitor core contact structure consists of a first core conductor electrically connected to the peripheral circuit and a first cover insulating layer extending between the first core conductor and the gate electrodes, forming a capacitor.
- The patent describes a vertically-integrated nonvolatile memory device with a unique cell array structure and peripheral circuit structure.
- The cell area of the device contains gate electrodes and insulating layers stacked alternately, while the connection area includes capacitor core contact structures and capacitor gate contact structures.
- The gate electrodes have a staircase shape and are connected to a cell stack, providing a unique design feature.
- Each capacitor core contact structure consists of a first core conductor and a first cover insulating layer, forming a capacitor with the gate electrodes.
- The device is bonded to the peripheral circuit structure, allowing for efficient integration and operation.
Potential applications of this technology:
- Nonvolatile memory devices are widely used in various electronic devices, such as smartphones, tablets, and computers. This vertically-integrated nonvolatile memory device can be applied in these devices to enhance their storage capabilities.
- The unique design features of the device, such as the staircase-shaped gate electrodes and the capacitor core contact structures, can improve the performance and reliability of nonvolatile memory devices.
Problems solved by this technology:
- The vertically-integrated nonvolatile memory device solves the problem of limited storage capacity in electronic devices by providing an efficient and compact memory solution.
- The unique design features of the device address issues related to performance and reliability, ensuring optimal operation and data retention.
Benefits of this technology:
- The vertically-integrated nonvolatile memory device offers increased storage capacity, allowing for the storage of larger amounts of data in electronic devices.
- The unique design features of the device improve performance and reliability, resulting in faster data access and reduced data loss.
- The efficient integration of the device with the peripheral circuit structure simplifies the manufacturing process and reduces production costs.
Original Abstract Submitted
A vertically-integrated nonvolatile memory device includes a peripheral circuit structure with a peripheral circuit therein, and cell array structure that is bonded to the peripheral circuit structure, and has a cell area and a connection area therein. The cell area includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked, in the connection area. The plurality of gate electrodes include a cell stack having a staircase shape, a plurality of capacitor core contact structures configured to pass through the cell stack in the cell area, and a plurality of capacitor gate contact structures connected to the plurality of gate electrodes in the connection area. Each of the plurality of capacitor core contact structures includes: (i) a first core conductor electrically connected to the peripheral circuit, and (ii) a first cover insulating layer extending between the first core conductor and the plurality of gate electrodes, and constitutes a capacitor in which the first core conductor, the first cover insulating layer, and the plurality of gate electrodes are connected to the peripheral circuit.
