18301706. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Jun Yun Kweon of Suwon-si (KR)

Yeong Beom Ko of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18301706 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The abstract of the patent application describes a semiconductor package that includes multiple semiconductor chips and dummy chips. The package also includes through vias that penetrate the chips and are electrically connected to each other. Bonding pads are used to connect the chips together, and an insulating layer is present below the chips.

• The semiconductor package includes multiple semiconductor chips and dummy chips.
• Through vias penetrate the chips and are electrically connected to each other.
• Bonding pads are used to connect the chips together.
• An insulating layer is present below the chips.

Potential Applications:

• This technology can be used in various electronic devices that require multiple semiconductor chips to be connected and integrated.
• It can be applied in the manufacturing of microprocessors, memory chips, and other complex integrated circuits.

Problems Solved:

• The semiconductor package solves the problem of connecting and integrating multiple semiconductor chips in a compact and efficient manner.
• It provides a solution for ensuring electrical connectivity between the chips and preventing interference or short circuits.

Benefits:

• The semiconductor package allows for higher levels of integration and miniaturization in electronic devices.
• It improves the performance and functionality of electronic devices by enabling efficient communication between multiple semiconductor chips.
• The package design helps in reducing the overall size and weight of electronic devices, making them more portable and convenient.

Original Abstract Submitted

A semiconductor package includes a first semiconductor chip, first and second dummy chips below the first semiconductor chip, a second semiconductor chip between the first and second dummy chips, a first through via penetrating the second semiconductor chip and electrically connected to the first semiconductor chip, second and third through vias penetrating the first and second dummy chips, respectively, and each electrically connected to the first semiconductor chip, a first bonding pad bonding the first semiconductor chip to the second semiconductor chip, a second bonding pad bonding the first semiconductor chip to the first dummy chip, a third bonding pad bonding the first semiconductor chip to the second dummy chip, and a first insulating layer below the second semiconductor chip and below the first and second dummy chips with each of the first, second, and third through vias penetrating the first insulating layer.