18237815. DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY simplified abstract (Micron Technology, Inc.)
DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY
Organization Name
Inventor(s)
Jiewei Chen of Meridian ID (US)
Mithun Kumar Ramasahayam of Meridian ID (US)
Tomoko Ogura Iwasaki of San Jose CA (US)
DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18237815 titled 'DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY
Simplified Explanation
Control logic in a memory device applies a pass voltage to multiple wordlines in a block of a memory array, boosting the channel potential of each sub-block to a boost voltage. The control logic then selectively discharges the boost voltage from one or more sub-blocks based on a data pattern for programming memory cells in the sub-blocks. A single programming pulse is applied to a selected wordline to program the memory cells in the sub-blocks according to the data pattern.
- Pass voltage applied to wordlines in memory array block
- Boosts channel potential of sub-blocks to boost voltage
- Selectively discharges boost voltage based on data pattern
- Single programming pulse applied to selected wordline for programming memory cells
Potential Applications
- Memory devices
- Data storage systems
- Solid-state drives
Problems Solved
- Efficient programming of memory cells
- Improved data storage performance
- Enhanced memory array functionality
Benefits
- Faster programming of memory cells
- More precise data pattern programming
- Increased memory array efficiency
Original Abstract Submitted
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.
