18235183. ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE simplified abstract (Micron Technology, Inc.)

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ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE

Organization Name

Micron Technology, Inc.

Inventor(s)

Ching-Huang Lu of Fremont CA (US)

Vinh Quang Diep of Hayward CA (US)

Avinash Rajagiri of Boise ID (US)

Yingda Dong of Los Altos CA (US)

ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18235183 titled 'ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE

Simplified Explanation

The abstract describes a control logic for initiating an erase operation in a memory device, involving a series of erase loops to erase memory cells.

  • During the first erase loop, a first erase pulse with a specific voltage level is applied to the source line of the memory cells.
  • A first erase bias voltage is applied to the first select gate and a second erase bias voltage is applied to the second select gate, both based on a delta voltage level.
  • In subsequent erase loops, a second erase pulse with the same voltage level is applied to the source line.
  • Adjusted erase bias voltages are applied to the select gates during these subsequent loops.

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      1. Potential Applications
  • Data storage devices
  • Embedded systems
  • Solid-state drives
      1. Problems Solved
  • Efficient erasing of memory cells
  • Control logic for erase operations
  • Voltage level adjustments for bias voltages
      1. Benefits
  • Improved memory device performance
  • Enhanced reliability
  • Simplified erase operation control


Original Abstract Submitted

Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. During the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.

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