18234429. MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL simplified abstract (Micron Technology, Inc.)
Contents
MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL
Organization Name
Inventor(s)
Massimo Ernesto Bertuccio of San Donato Milanese (IT)
Sead Zildzic, Jr. of Folsom CA (US)
MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL - A simplified explanation of the abstract
This abstract first appeared for US patent application 18234429 titled 'MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL
Simplified Explanation
The patent application describes a memory device with an array of memory cells, access lines, and a controller. The memory cells are organized in strings of series-connected cells, each accessed by a control gate through access lines. The controller can program a selected memory cell to a target level by applying different voltage levels to the access lines.
- Memory device with array of memory cells
- Memory cells organized in strings of series-connected cells
- Access lines connect to control gates of memory cells
- Controller can program selected memory cell to target level
- Different voltage levels applied to access lines for programming
- Potential Applications
- Data storage devices - Embedded systems - Consumer electronics
- Problems Solved
- Efficient memory cell programming - Improved data storage capabilities - Enhanced performance in memory devices
- Benefits
- Faster data access - Higher storage capacity - Increased reliability in memory operations
Original Abstract Submitted
A memory device includes an array of memory cells, a plurality of access lines, and a controller. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line is connected to a control gate of a respective memory cell of each string of series-connected memory cells. The controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level. The controller is further configured to apply a first voltage level to a first access line connected to the selected memory cell, and apply a second voltage level higher than the first voltage level to a second access line adjacent to the first access line. The controller is further configured to apply a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell, and sense a first threshold voltage of the selected memory cell.
