18234129. CONTACT ARRANGEMENTS FOR TRANSISTORS simplified abstract (Micron Technology, Inc.)
Contents
CONTACT ARRANGEMENTS FOR TRANSISTORS
Organization Name
Inventor(s)
Yoshikazu Moriwaki of Hiroshima (JP)
CONTACT ARRANGEMENTS FOR TRANSISTORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18234129 titled 'CONTACT ARRANGEMENTS FOR TRANSISTORS
Simplified Explanation
- Apparatus with transistors have contact arrangements to reduce parasitic capacitance between contacts and gate.
- Contacts to active areas positioned beyond boundaries of gate ends along a direction.
- Metal silicide region couples contacts in active region positioned beyond gate boundaries along a direction.
Potential Applications
- Integrated circuits
- Semiconductor devices
- Electronics industry
Problems Solved
- Mitigation of parasitic capacitance
- Improved performance of transistors
- Enhanced efficiency of electronic devices
Benefits
- Increased speed and reliability of electronic devices
- Reduction in power consumption
- Enhanced overall performance of integrated circuits
Original Abstract Submitted
A variety of applications can include apparatus having one or more transistors with a contact arrangement to significantly mitigate a parasitic capacitance between one or more contacts to an active area of the transistor and a gate of the transistor. One or more contact arrangements can include a contact to an active area in a position beyond a boundary of an end of the gate along a first direction, where the gate is structured along the first direction. One or more other contact arrangements can include two contacts to an active area in positions beyond boundaries of two opposite ends of the gate along a first direction. Arrangements can include a metal silicide region coupling two contacts to each other in an active region with the two contacts in positions beyond boundaries of two opposite ends of the gate along a first direction.
