18232706. MEMORY WITH DETERMINISTIC WORST-CASE ROW ADDRESS SERVICING, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS simplified abstract (Micron Technology, Inc.)
MEMORY WITH DETERMINISTIC WORST-CASE ROW ADDRESS SERVICING, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Organization Name
Inventor(s)
Randall J. Rooney of Boise ID (US)
MEMORY WITH DETERMINISTIC WORST-CASE ROW ADDRESS SERVICING, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18232706 titled 'MEMORY WITH DETERMINISTIC WORST-CASE ROW ADDRESS SERVICING, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Simplified Explanation
The patent application describes a method for managing memory in a memory device with deterministic worst-case row address servicing. Here is a simplified explanation of the abstract:
- Updating counter values for memory rows based on row activations
- Comparing updated counter values to worst-case count values
- Setting worst-case count values and storing worst-case memory row addresses
- Performing row disturb refresh operations using worst-case memory row addresses
Potential Applications of this Technology: - Memory management in high-performance computing systems - Real-time data processing applications - Embedded systems with strict timing requirements
Problems Solved by this Technology: - Ensuring deterministic worst-case row address servicing - Optimizing memory access for critical applications - Preventing memory access delays in high-throughput systems
Benefits of this Technology: - Improved reliability and predictability in memory access - Enhanced performance for time-sensitive applications - Efficient memory utilization in high-demand scenarios
Potential Commercial Applications of this Technology: - Data centers and cloud computing facilities - Automotive electronics for advanced driver assistance systems - Aerospace and defense systems for mission-critical operations
Possible Prior Art: - Existing memory management techniques in high-performance computing - Previous methods for optimizing memory access in embedded systems
Unanswered Questions: Title: How does this method compare to existing memory management techniques? Answer: A comparative analysis with current memory management methods could provide insights into the advantages of this technology in specific use cases.
Title: What are the potential limitations or drawbacks of this method? Answer: Understanding any constraints or challenges associated with implementing this method could help in assessing its applicability in different scenarios.
Original Abstract Submitted
Memory with deterministic worst-case row address servicing is disclosed herein. A method of the present technology comprises (1) updating a counter value corresponding to a memory row of a memory device in response to detecting activation of the memory row; (2) comparing the updated counter value to a worst-case count value; and (3) in response to determining that the updated counter value is greater than the worst-case count value, setting the worst-case count value equal to the updated counter value and storing a memory row address of the memory row as a worst-case memory row address. The counter value can be one of a plurality of counter values, each counter value (a) corresponding to a respective memory row and (b) configured to track a number of activations of the respective memory row. The method can further comprise performing a row disturb refresh operation using the worst-case memory row address.
