18211472. TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK simplified abstract (Micron Technology, Inc.)
Contents
- 1 TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK
Organization Name
Inventor(s)
Wolfgang Anton Spirkl of Germering (DE)
Michael Dieter Richter of Ottobrunn (DE)
TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK - A simplified explanation of the abstract
This abstract first appeared for US patent application 18211472 titled 'TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK
Simplified Explanation
The patent application describes systems, apparatuses, and methods for transmission failure feedback associated with a memory device. Here are some key points to explain the innovation:
- Memory device detects errors in received data and transmits an indication of the error when detected.
- Memory device receives data and checksum information from a controller.
- Memory device generates a checksum for the received data and detects transmission errors.
- Memory device transmits an indication of detected errors to the controller using a different line than the error detection code (EDC) line.
- A low-speed tracking clock signal is transmitted by the memory device over a line different than the EDC line.
- Memory device transmits a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
Potential Applications
The technology described in the patent application could be applied in various industries such as data storage, telecommunications, and computer hardware manufacturing.
Problems Solved
This technology helps in improving data transmission reliability by providing feedback on transmission failures, allowing for timely error detection and correction.
Benefits
The benefits of this technology include enhanced data integrity, improved system performance, and increased reliability in data transmission processes.
Potential Commercial Applications
The technology could be commercially applied in the development of memory devices, data storage systems, and communication networks.
Possible Prior Art
One possible prior art for this technology could be error detection and correction mechanisms used in data storage devices and communication systems.
Unanswered Questions
How does this technology compare to existing error detection and correction mechanisms in terms of efficiency and accuracy?
This article does not provide a direct comparison with existing mechanisms, so it is unclear how this technology stacks up against current solutions.
What are the potential limitations or challenges in implementing this technology on a large scale in real-world applications?
The article does not address potential challenges or limitations that may arise when implementing this technology in practical, large-scale settings.
Original Abstract Submitted
Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
