18169635. SELECTIVE PER DIE DRAM PPR FOR CXL TYPE 3 DEVICE simplified abstract (Micron Technology, Inc.)

SELECTIVE PER DIE DRAM PPR FOR CXL TYPE 3 DEVICE

Organization Name

Micron Technology, Inc.

Inventor(s)

Amitava Majumdar of Boise ID (US)

Greg S. Hendrix of Boise ID (US)

Anandhavel Nagendrakumar of Boise ID (US)

Krunal Patel of Boise ID (US)

Kirthi Shenoy of Boise ID (US)

Danilo Caraccio of Milano (IT)

Ankush Lal of Boise ID (US)

Frank F. Ross of Boise ID (US)

Adam D. Gailey of Boise ID (US)

SELECTIVE PER DIE DRAM PPR FOR CXL TYPE 3 DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18169635 titled 'SELECTIVE PER DIE DRAM PPR FOR CXL TYPE 3 DEVICE

Simplified Explanation

The abstract describes a system and method for identifying and repairing memory errors in rows of DRAM memory in a CXL memory controller system.

• When data is written to a row of DRAM, it is immediately read back and scanned for bit errors.
• If bit errors are found, the system determines if the memory location requires no repair, soft repair, or hard repair.
• The data is corrected and written back to a new memory location that is memory-mapped to the original location, effecting the repair.
• Only the specific die(s) that exhibit memory errors in the row are repaired, not the entire row of memory.

Potential Applications

This technology could be applied in high-performance computing systems, data centers, and other memory-intensive applications where memory errors need to be quickly identified and repaired.

Problems Solved

1. Efficient identification and repair of memory errors in DRAM memory. 2. Minimizing the impact of memory errors on system performance and reliability.

Benefits

1. Improved system reliability and uptime. 2. Enhanced memory error detection and correction capabilities. 3. Cost-effective repair solutions for memory errors.

Potential Commercial Applications

Optimizing memory performance in servers, supercomputers, and other high-end computing systems.

Possible Prior Art

One possible prior art could be memory error correction techniques used in traditional memory systems, but the specific approach of identifying and repairing errors at the die level in a CXL memory controller system may be novel.

Unanswered Questions

How does the system determine if a memory location requires no repair, soft repair, or hard repair?

The abstract does not provide details on the specific criteria or algorithms used to make this determination.

What are the potential limitations or drawbacks of this system and method?

The abstract does not mention any potential limitations or drawbacks of the proposed system and method.

Original Abstract Submitted

In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.