18151622. PACKAGED MULTI-CHIP SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
PACKAGED MULTI-CHIP SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME
Organization Name
Inventor(s)
Hyuekjae Lee of Hwaseong-si (KR)
Jongho Lee of Hwaseong-si (KR)
Sangcheon Park of Hwaseong-si (KR)
Jinkyeong Seol of Cheonan-si (KR)
Sanghoon Lee of Seongnam-si (KR)
PACKAGED MULTI-CHIP SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18151622 titled 'PACKAGED MULTI-CHIP SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME
Simplified Explanation
The abstract describes a semiconductor package that includes multiple layers and structures to connect and protect semiconductor chips.
- The package includes a first connection structure, which serves as a base for the other components.
- A first semiconductor chip is placed on the upper surface of the first connection structure.
- A first molding layer surrounds the first semiconductor chip, providing protection and support.
- A first bond pad is located on the first semiconductor chip, allowing for electrical connections.
- A first bond insulation layer surrounds the first bond pad, preventing electrical interference.
- A second bond pad is directly connected to the first bond pad.
- A second bond insulation layer surrounds the second bond pad.
- A second semiconductor chip is placed on the second bond pad and the second bond insulation layer.
Potential applications of this technology:
- Integrated circuits
- Microprocessors
- Memory devices
- Power devices
Problems solved by this technology:
- Provides a secure and reliable connection between semiconductor chips
- Protects the chips from external factors such as moisture and physical damage
- Reduces the risk of electrical interference
Benefits of this technology:
- Improved performance and reliability of semiconductor devices
- Enhanced durability and longevity of the chips
- Enables miniaturization and compact designs
Original Abstract Submitted
A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.
